MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 48
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 48 of 1340
- Download datasheet (12Mb)
Figure
Number
7-14
7-15
7-16
7-17
7-18
7-19
7-20
7-21
7-22
7-23
7-24
7-25
7-26
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
xlviii
L2 Error Injection Mask Low Register (L2ERRINJLO) ...................................................... 7-18
L2 Error Injection Mask Control Register (L2ERRINJCTL) ............................................... 7-19
L2 Error Capture Data High Register (L2CAPTDATAHI)................................................... 7-20
L2 Error Capture Data Low Register (L2CAPTDATALO) .................................................. 7-20
L2 Error Syndrome Register (L2CAPTECC) ....................................................................... 7-20
L2 Error Detect Register (L2ERRDET) ............................................................................... 7-21
L2 Error Disable Register (L2ERRDIS) ............................................................................... 7-22
L2 Error Interrupt Enable Register (L2ERRINTEN) ........................................................... 7-22
L2 Error Attributes Capture Register (L2ERRATTR) .......................................................... 7-23
L2 Error Address Capture Register (L2ERRADDRH)......................................................... 7-24
L2 Error Address Capture Register (L2ERRADDRL) ......................................................... 7-25
L2 Error Control Register (L2ERRCTL).............................................................................. 7-25
L2 Cache Line Replacement Algorithm ............................................................................... 7-31
e500 Coherency Module Block Diagram................................................................................ 8-1
ECM CCB Address Configuration Register (EEBACR)........................................................ 8-3
ECM CCB Port Configuration Register (EEBPCR)............................................................... 8-4
ECM IP Block Revision Register 1 (EIPBRR1)..................................................................... 8-5
ECM IP Block Revision Register 2 (EIPBRR2)..................................................................... 8-5
ECM Error Detect Register (EEDR)....................................................................................... 8-6
ECM Error Enable Register (EEER) ...................................................................................... 8-7
ECM Error Attributes Capture Register (EEATR) ................................................................. 8-7
ECM Error Low Address Capture Register (EELADR)......................................................... 8-8
ECM Error High Address Capture Register (EEHADR)........................................................ 8-9
DDR Memory Controller Simplified Block Diagram............................................................. 9-2
Chip Select Bounds Registers (CSn_BNDS)........................................................................ 9-11
Chip Select Configuration Register (CSn_CONFIG) ........................................................... 9-12
DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) ................................................ 9-13
DDR SDRAM Timing Configuration 0 (TIMING_CFG_0) ................................................ 9-14
DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) ................................................ 9-16
DDR SDRAM Timing Configuration 2 Register (TIMING_CFG_2).................................. 9-18
DDR SDRAM Control Configuration Register (DDR_SDRAM_CFG) .............................. 9-20
DDR SDRAM Control Configuration Register 2 (DDR_SDRAM_CFG_2)....................... 9-23
DDR SDRAM Mode Configuration Register (DDR_SDRAM_MODE)............................. 9-25
DDR SDRAM Mode 2 Configuration Register (DDR_SDRAM_MODE_2)...................... 9-26
DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL) ................................ 9-26
DDR SDRAM Interval Configuration Register (DDR_SDRAM_INTERVAL) .................. 9-29
DDR SDRAM Data Initialization Configuration Register (DDR_DATA_INIT)................. 9-29
DDR SDRAM Clock Control Configuration
DDR Initialization Address Configuration Register (DDR_INIT_ADDR) ......................... 9-31
Register (DDR_SDRAM_CLK_CNTL).......................................................................... 9-30
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
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