MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 273

Manufacturer Part Number

BOARD DEVELOPMENT SYSTEM 8544

Manufacturer

Freescale Semiconductor

PowerQUICC III™r

Processor To Be Evaluated

Data Bus Width

Interface Type

Ethernet, I2C

Operating Supply Voltage

- 0.3 V to + 1.1 V

Leaded Process Compatible

Peak Reflow Compatible (260 C)

Rohs Compliant

For Use With/related Products

For Use With

PPC8544EVTANG - EVAL MPC8544 783FCPBGA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

SRAM features include the following:

Freescale Semiconductor

Error injection modes supported for testing error handling

SRAM regions are created by configuring 1, 2, 4 or 8 ways of each set to be reserved for

memory-mapped SRAM.

Regions can reside at any location in the memory map aligned to the SRAM size.

SRAM memory is byte addressable; for accesses of less than a cache line, ECC is updated using

read-modify-write transactions.

I/O devices access SRAM regions by marking transactions as snoopable (global).

lists the possible L2 cache/SRAM configurations.

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

Table 1. Available L2 Cache/SRAM Configurations

Stash-only Region

SRAM Region 1

SRAM Region 2

L2 Look-Aside Cache/SRAM