MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 62

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure
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18-13
18-14
18-15
18-16
18-17
18-18
18-19
18-20
18-21
18-22
18-23
18-24
18-25
18-26
18-27
18-28
18-29
18-30
18-31
18-32
18-33
18-34
18-35
18-36
18-37
18-38
18-39
18-40
18-41
18-42
18-43
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RC Outbound Transaction Flow ......................................................................................... 18-20
PCI Express Outbound Translation Address Registers (PEXOTARn) ............................... 18-20
PCI Express Outbound Translation Extended Address
PCI Express Outbound Window Base Address Registers (PEXOWBARn) ...................... 18-21
PCI Express Outbound Window Attributes Register 0 (PEXOWAR0).............................. 18-22
PCI Express Outbound Window Attributes Registers 1–4 (PEXOWARn) ........................ 18-22
RC Inbound Transaction Flow ............................................................................................ 18-25
PCI Express Inbound Translation Address Registers (PEXITARn) ................................... 18-25
PCI Express Inbound Window Base Address Registers (PEXIWBARn)........................... 18-26
PCI Express Inbound Window Base Extended Address
PCI Express Inbound Window Attributes Registers (PEXIWARn).................................... 18-27
PCI Express Error Detect Register (PEX_ERR_DR) ......................................................... 18-30
PCI Express Error Interrupt Enable Register (PEX_ERR_EN).......................................... 18-32
PCI Express Error Disable Register (PEX_ERR_DISR).................................................... 18-34
PCI Express Error Capture Status Register (PEX_ERR_CAP_STAT)............................... 18-35
PCI Express Error Capture Register 0 (PEX_ERR_CAP_R0)
PCI Express Error Capture Register 0 (PEX_ERR_CAP_R0)
PCI Express Error Capture Register 1 (PEX_ERR_CAP_R1)
PCI Express Error Capture Register 1 (PEX_ERR_CAP_R1)
PCI Express Error Capture Register 2 (PEX_ERR_CAP_R2)
PCI Express Error Capture Register 2 (PEX_ERR_CAP_R2)
PCI Express Error Capture Register 3 (PEX_ERR_CAP_R3)
PCI Express Error Capture Register 3 (PEX_ERR_CAP_R3)
PCI Express PCI-Compatible Configuration Header Common Registers.......................... 18-43
PCI Express Vendor ID Register......................................................................................... 18-44
PCI Express Device ID Register ......................................................................................... 18-44
PCI Express Command Register......................................................................................... 18-45
PCI Express Status Register................................................................................................ 18-46
PCI Express Revision ID Register ...................................................................................... 18-47
PCI Express Class Code Register ....................................................................................... 18-48
PCI Express Bus Cache Line Size Register ........................................................................ 18-48
Registers (PEXOTEARn) .............................................................................................. 18-21
Registers (PEXIWBEARn) ............................................................................................ 18-27
Internal Source, Outbound Transaction.......................................................................... 18-36
External Source, Inbound Transaction ........................................................................... 18-37
Internal Source, Outbound Transaction.......................................................................... 18-38
External Source, Inbound Transaction ........................................................................... 18-38
Internal Source, Outbound Transaction.......................................................................... 18-39
External Source, Inbound Transaction ........................................................................... 18-40
Internal Source, Outbound Transaction.......................................................................... 18-41
External Source, Inbound Transaction ........................................................................... 18-41
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
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