MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 846

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
Table 15-108
15.5.3.10.2 Receive Free Buffer Descriptor Pointer Registers 0–7
The RFBPTRn registers specify the location of the last free buffer descriptor in their respective ring. These
registers live in the same 32b address space – and must share the same 4 most significant bits – as RBPTRn.
That is, RFBPTRn and its associated RBPTRn must remain in the same 256MB page. Like RBPTRn,
whenever RBASEn is updated, RFBPTRn will be initialized to the value of RBASEn. This indicates that
the ring is completely empty. As buffers are freed and their respective BDs are returned (by setting the
EMPTY bit) to the ring, software is expected to update this register. The eTSEC will then perform modulo
arithmetic involving RBASEn, RBPTRn and RFBPTRn to determine the number of free BDs remaining
in the ring. If, at any stage, the value written to RFBPTRn matches that of the respective RBPTRn the
eTSEC free BD calculation will assume that the ring is now completely empty. For more information on
the recommended use of these registers, see
Buffers.”
15-114
Offset eTSEC1:0x2_4C00+4× n ; eTSEC3:0x2_5C00+4× n
Reset
Offset eTSEC1:0x2_4C40+8× n ; eTSEC3:0x2_5C40+8× n
Reset
8–31
Bits
0–7
W
W
R
R
0
0
Figure 15-106
FBTHR Free BD threshold. Minimum number of BDs required for normal operation. If the eTSEC calculated
Name
LEN
describes the fields of the RQPRM register.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
(RFBPTR0–RFBPTR7)
FBTHR
number of free BDs drops below this threshold, link layer flow control will be asserted.
Ring length. Total number of Rx BDs in this ring.
describes the definition for the RFBPTRn register.
Figure 15-106. RFBPTR0–RFBPTR7 Register Definition
7
Figure 15-105. RQPRM Register Definition
Table 15-108. RQPRM Field Descriptions
8
Section 15.6.6.1, “Back Pressure Determination via Free
RFBPTR n
All zeros
All zeros
Description
LEN
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
28 29
—
31
31