MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 173

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.4.3.6
The MPC8544E can be configured with different I/O ports active.
I/O ports and bit rates (and required reference clocks) that are possible for the PCI Express interfaces.
Freescale Semiconductor
TSEC3_TXD[6:4]
Default (111)
Functional
Signal
I/O Port Selection
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reset Configuration
cfg_IO_ports[0:2]
Name
Table 4-14. I/O Port Selection
(Binary)
Value
000
001
010
011
100
101
All three PCI Express ports powered down
SGMII ports powered down
All three PCI Express ports powered down
SGMII ports active
PCI Express port 1active
PCI Express ports 2 and 3 powered down
PCI Express 1:
RX lane[0:3] → SD1_RX[0:3],
TX lane[0:3] → SD1_TX[0:3]
SGMII ports powered down
PCI Express port 1active
PCI Express ports 2 and 3 powered down
PCI Express 1:
RX lane[0:3] → SD1_RX[0:3],
TX lane[0:3] → SD1_TX[0:3]
SGMII ports active
PCI Express ports 1 and 2 active
PCI Express port 3 powered down
PCI Express 1:
RX lane[0:3] → SD1_RX[0:3],
TX lane[0:3] → SD1_TX[0:3]
PCI Express 2:
RX lane[0:3] → SD1_RX[4:7],
TX lane[0:3] → SD1_TX[4:7]
SGMII ports powered down
PCI Express ports 1 and 2 active
PCI Express port 3 powered down
PCI Express 1:
RX lane[0:3] → SD1_RX[0:3],
TX lane[0:3] → SD1_TX[0:3]
PCI Express 2:
RX lane[0:3] → SD1_RX[4:7],
TX lane[0:3] → SD1_TX[4:7]
SGMII ports active
Table 4-14
Meaning
shows the configuration of
Reset, Clocking, and Initialization
4-15