MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 1028
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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PCI Bus Interface
The low-priority group collectively has one bus transaction request slot in the high-priority group. For N
high-priority devices and M low-priority devices, each high-priority device is guaranteed at least 1 of N+1
bus transactions and each low-priority device is guaranteed at least 1 of (N+1) × M bus transactions, with
one low-priority device receiving the grant in 1 of N+1 bus transactions. If all devices are programmed to
the same priority level, or if the low-priority group has only one device, the algorithm defaults to give each
device an equal number of bus grants in round-robin sequence.
For the example in
Figure
17-48, assume that several devices are requesting the bus. If two masters are in
the high-priority group and three are in the low-priority group, each high-priority master is guaranteed at
least one out of three transaction slots and each low-priority master is guaranteed one out of nine
transaction slots.
In
Figure
17-48, the grant sequence (with all devices, except device 4 requesting the bus and device 3
being the current master) is 0, 2, MPC8544E, 0, 2, 1, 0, 2, 3, …, and repeating. If device 2 is not requesting
the bus, the grant sequence is 0, MPC8544E, 0, 1, 0, 3, …, and repeating. If device 2 requests the bus when
device 0 is conducting a transaction and the MPC8544E has the next grant, the MPC8544E has its grant
removed and device 2 is awarded the grant since device 2 is higher priority than the MPC8544E when
device 0 has the bus.
High-Priority Group
Low-Priority Group
Device 2
Device 1
(1/3)
(1/9)
Low-
Priority
PQIII
Device 0
Device 3
Slot
(1/3)
(1/9)
(1/9)
(1/3)
Figure 17-48. PCI Arbitration Example
17.4.1.2
PCI Bus Parking
When no device is using or requesting the bus, the PCI arbiter grants the bus to a selected device. This is
known as parking the bus on the selected device. The selected device is required to drive the
PCI_AD[31:0], PCI_C/BE[0:3], and the PCI parity signals to a stable value, preventing these signals from
floating.
The parking mode parameter (PBACR[PM]) determines which device the arbiter selects for parking the
PCI bus. If PBACR[PM] = 0 (or if the bus is not idle), then the bus is parked on the last master to use the
bus. If the bus is idle and PBACR[PM] = 1, the bus is parked on the PCI controller.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
17-44
Freescale Semiconductor
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