MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 407
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
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- MPC8544VTALF PDF datasheet #3
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10.3
The PIC programmable register map occupies 256 Kbytes of memory-mapped space. Reading undefined
portions of the memory map returns all zeros; writing has no effect.
All PIC registers are 32 bits wide and, although located on 128-bit address boundaries, should only be
accessed as 32-bit quantities.
The PIC address offset map, shown in
In the following table and in the register figures and field descriptions, the following access definitions
apply:
Freescale Semiconductor
0x4_00C0–
0x4_0020–
0x4_0000 BRR1—Block revision register 1
0x4_0010 BRR2—Block revision register 2
0x4_0030
0x4_0040 IPIDR0—Interprocessor interrupt 0 (IPI 0) dispatch register
0x4_0050 IPIDR1—Interprocessor interrupt 1 (IPI 1) dispatch register
0x4_0060 IPIDR2—Interprocessor interrupt 2 (IPI 2) dispatch register
0x4_0070 IPIDR3—Interprocessor interrupt 3 (IPI 3) dispatch register
0x4_0080 CTPR—Current task priority register
0x4_0090 WHOAMI—Who am I register
0x4_00A0 IACK—Interrupt acknowledge register
0x4_00B0 EOI—End of interrupt register
0x4_0FF0
0x4_1000 FRR—Feature reporting register
Offset
•
•
•
•
•
•
•
•
0xnn4_0000–0xnn4_FFF0—Global registers
0xnn5_0000–0xnn5_FFF0—Interrupt source configuration registers
0xnn6_0000–0xnn7_FFF0—Per-CPU registers
Reserved fields are always ignored for the purposes of determining access type.
R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
Mixed indicates a combination of access types.
Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
Reserved
Reserved
Memory Map/Register Definition
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PIC Register Address Map—Global Registers
Table 10-6. PIC Register Address Map
Register
Table
10-6, is divided into three areas:
Access
R/W
—
W
W
—
R
R
R
R
R
Programmable Interrupt Controller
0x0040_0200
0x0000_0001
0x0000_0000
0x0000_000F
0x0000_0000
0x0000_0000
0x0000_0000
0x004F_0002
Reset
—
—
10.3.1.1/10-18
10.3.1.2/10-19
10.3.8.1/10-45
10.3.8.2/10-46
10.3.8.3/10-47
10.3.8.4/10-47
10.3.8.5/10-48
10.3.1.3/10-19
Section/Page
—
—
10-9
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