MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 286
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
L2 Look-Aside Cache/SRAM
7.3.1.3.1
The L2 memory-mapped SRAM base address registers (L2SRBARn), shown in
lower 18 bits of the 22-bit SRAM base address.
L2SRBAR bits are described in
When enabled, the windows defined in L2SRBARn and L2SRBAREAn supersede all other mappings of
these addresses for processor and global (snoopable) I/O transactions. Therefore, SRAM windows must
never overlap configuration space as defined by CCSRBAR (see
Control, and Status Base Address Register
is discouraged because processor and snoopable I/O transactions would map to the SRAM while
non-snooped I/O transactions would be mapped by the local access windows. Only if all accesses to the
SRAM address range are snoopable can results be consistent if SRAM and local access windows overlap.
7-16
18–31
Offset 0x2_0100
0–17
Reset
Bits
W
R
0x2_0108
0
ADDR Contains the lower 18 bits of the 22-bit L2 memory-mapped SRAM base address; the upper 4 bits are
Name
—
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure 7-11. L2 Memory-Mapped SRAM Base Address Registers (L2SRBAR n )
contained in L2SRBAREA n [ADDR]. (Note that some of these bits may not be needed, depending on how the
L2 cache is partitioned.) The combined base address from L2SRBAREA n [ADDR] || L2SRBAR n [ADDR] is
used as follows:
SRAM Partition
64 Kbytes
128 Kbytes
256 Kbytes
Unused bits of the base address are masked off by the hardware.
Reserved
L2 Memory-Mapped SRAM Base Address Registers 0–1 (L2SRBAR n )
Bits Required for SRAM Offset
ADDR
Table
Table 7-8. L2SRBAR n Field Descriptions
16
17
18
7-8.
(CCSRBAR).”) Overlapping SRAM and local access windows
All zeros
Description
17 18
Bits Used for Actual Base Address
20 (0–19)
19 (0–18)
18 (0–17)
Section 4.3.1.1.2, “Configuration,
Figure
—
Freescale Semiconductor
Access: Read/Write
7-11, contain the
31
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