MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 935

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
read the MII Mgmt AN Link Partner Base Page Ability register and check bits 9 and 10. (Half and Full Duplex)
MII Mgmt AN Link Partner Base Page Ability ---> [0000_0000_0000_0000_0000_00x_x110_0000]
read the MII Mgmt AN Expansion register and check bits 13 and 14. (NP Able and Page Rx’d)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Perform an MII Mgmt read cycle of AN Link Partner Base Page Ability Register. (Optional)
(Uses the PHY address (0x10) and Register address (6) placed in MIIMADD register),
(Uses the PHY address (0x10) and Register address (5) placed in MIIMADD register),
MII Mgmt AN Expansion ---> [0000_0000_0000_0000_0000_0000_0000_0110]
Table 15-165. RTBI Mode Register Initialization Steps (continued)
RBASE0–RBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
TBASE0–TBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
Setup MIIMADD[0000_0000_0000_0000_0001_0000_0000_0110]
Setup MIIMADD[0000_0000_0000_0000_0001_0000_0000_0101]
Initialize (Empty) Receive Descriptor ring and fill with empty buffers
MACnADDR1/2[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize (Empty) Transmit Descriptor ring and fill buffers with Data
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101]
DMACTRL[0000_0000_0000_0000_0000_0000_0000_0000]
GADDR n [0000_0000_0000_0000_0000_0000_0000_0000]
Perform an MII Mgmt read cycle of AN Expansion Register.
IEVENT[0000_0000_0000_0000_0000_0000_0000_0000]
RCTRL[0000_0000_0000_0000_0000_0000_0000_0000]
IMASK[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize MACnADDR1/2 (Optional)
Initialize DMACTRL (Optional)
Clear MIIMCOM[Read Cycle]
Clear MIIMCOM[Read Cycle]
Initialize GADDR n (Optional)
Initialize RBASE0–RBASE7,
Initialize TBASE0–TBASE7,
Set MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
Initialize RCTRL (Optional)
When MIIMIND[BUSY]=0,
When MIIMIND[BUSY]=0,
Initialize IMASK (Optional)
Enable Transmit Queues
Enable Receive Queues
Clear IEVENT register,
Enable Rx and Tx,
Initialize RQUEUE
Initialize TQUEUE
Enhanced Three-Speed Ethernet Controllers
15-203