MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 16

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
10.3.1.6
10.3.1.7
10.3.1.8
10.3.2
10.3.2.1
10.3.2.2
10.3.2.3
10.3.2.4
10.3.2.5
10.3.2.6
10.3.3
10.3.3.1
10.3.3.2
10.3.3.3
10.3.3.4
10.3.3.5
10.3.3.6
10.3.3.7
10.3.4
10.3.4.1
10.3.4.2
10.3.4.3
10.3.5
10.3.5.1
10.3.5.2
10.3.5.3
10.3.6
10.3.6.1
10.3.6.2
10.3.6.3
10.3.6.4
10.3.6.5
10.3.7
10.3.7.1
10.3.7.2
10.3.7.3
10.3.7.4
10.3.7.5
10.3.7.6
10.3.8
10.3.8.1
xvi
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Global Timer Registers ............................................................................................ 10-23
External, IRQ_OUT, and Critical Interrupt Summary Registers............................. 10-28
Performance Monitor Mask Registers (PMMRs).................................................... 10-32
Message Registers.................................................................................................... 10-34
Shared Message Signaled Registers ........................................................................ 10-36
Interrupt Source Configuration Registers ................................................................ 10-39
Per-CPU Registers ................................................................................................... 10-44
IPI Vector/Priority Registers (IPIVPRn) ............................................................. 10-22
Spurious Vector Register (SVR).......................................................................... 10-23
Timer Frequency Reporting Register (TFRR)..................................................... 10-23
Global Timer Current Count Registers (GTCCRn) ............................................. 10-24
Global Timer Base Count Registers (GTBCRn).................................................. 10-24
Global Timer Vector/Priority Registers (GTVPRn)............................................. 10-25
Global Timer Destination Registers (GTDRn) .................................................... 10-26
Timer Control Register (TCR)............................................................................. 10-26
External Interrupt Summary Register (ERQSR) ................................................. 10-28
IRQ_OUT Summary Register 0 (IRQSR0) ......................................................... 10-29
IRQ_OUT Summary Register 1 (IRQSR1) ......................................................... 10-30
IRQ_OUT Summary Register 2 (IRQSR2) ......................................................... 10-30
Critical Interrupt Summary Register 0 (CISR0).................................................. 10-31
Critical Interrupt Summary Register 1 (CISR1).................................................. 10-31
Critical Interrupt Summary Register 2 (CISR2).................................................. 10-32
Performance Monitor n Mask Registers 0 (PMnMR0) ....................................... 10-32
Performance Monitor n Mask Registers 1 (PMnMR1) ....................................... 10-33
Performance Monitor n Mask Registers 2 (PMnMR2) ....................................... 10-34
Message Registers (MSGR0–MSGR3) ............................................................... 10-34
Message Enable Register (MER)......................................................................... 10-35
Message Status Register (MSR) .......................................................................... 10-35
Shared Message Signaled Interrupt Registers (MSIRs) ...................................... 10-36
Shared Message Signaled Interrupt Status Register (MSISR)............................. 10-36
Shared Message Signaled Interrupt Index Register (MSIIR) .............................. 10-37
Shared Message Signaled Interrupt Vector/Priority Register (MSIVPRn).......... 10-38
Shared Message Signaled Interrupt Destination Register (MSIDRn) ................. 10-38
External Interrupt Vector/Priority Registers (EIVPR0–EIVPR11) ..................... 10-39
External Interrupt Destination Registers (EIDR0–EIDR11) ............................... 10-40
Internal Interrupt Vector/Priority Registers (IIVPR0–IIVPR47)......................... 10-41
Internal Interrupt Destination Registers (IIDR0–IIDR47) .................................. 10-42
Messaging Interrupt Vector/Priority Registers (MIVPR0–MIVPR3) ................. 10-43
Messaging Interrupt Destination Registers (MIDR0–MIDR3) ........................... 10-43
Interprocessor Interrupt Dispatch Registers (IPIDR0–IPIDR3).......................... 10-45
Processor Initialization Register (PIR) ................................................................ 10-21
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