MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 339
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
Freescale Semiconductor
13–15
16–19
9–11
Bits
2–3
4–5
6–7
12
8
ACT_PD_EXIT Active powerdown exit timing (t
PRE_PD_EXIT Precharge powerdown exit timing (t
Name
WWT
WRT
RRT
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
—
—
—
Write-to-read turnaround. Specifies how many extra cycles will be added between a write to read
turnaround. If 0 clocks is chosen, then the DDR controller will use a fixed number based on the, read
latency, and write latency. Choosing a value other than 0 adds extra cycles past this default
calculation. As a default, the DDR controller will determine the write-to-read turnaround as WL – CL
+ BL/2 + 1. In this equation, CL is the CAS latency rounded down to the next integer, WL is the
programmed write latency, and BL is the burst length.
00 0 clocks
01 1 clock
Read-to-read turnaround. Specifies how many extra cycles will be added between reads to different
chip selects. As a default, 3 cycles will be required between read commands to different chip selects.
Extra cycles may be added with this field. Note: If 8-beat bursts are enabled, then 5 cycles will be
the default. Note that DDR2 does not support 8-beat bursts.
00 0 clocks
01 1 clock
Write-to-write turnaround. Specifies how many extra cycles will be added between writes to different
chip selects. As a default, 2 cycles will be required between write commands to different chip selects.
Extra cycles may be added with this field. Note: If 8-beat bursts are enabled, then 4 cycles will be
the default. Note that DDR2 does not support 8-beat bursts.
00 0 clocks
01 1 clock
Reserved, should be cleared.
exiting active powerdown before issuing any command.
000
001
010
011
Reserved, should be cleared.
precharge powerdown before issuing any command.
000 Reserved
001 1 clock
010 2 clocks
011 3 clocks
100 4 clocks
101 5 clocks
110 6 clocks
111 7 clocks
Reserved, should be cleared.
Table 9-9. TIMING_CFG_0 Field Descriptions (continued)
Reserved
1 clock
2 clocks
3 clocks
XARD
XP
and t
). Specifies how many clock cycles to wait after exiting
XARDS
Description
). Specifies how many clock cycles to wait after
10 2 clocks
11 3 clocks
10 2 clocks
11 3 clocks
10 2 clocks
11 3 clocks
100
101
110
111
4 clocks
5 clocks
6 clocks
7 clocks
DDR Memory Controller
9-15
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