MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 234
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
Core Register Summary
6.6.3
6.6.4
6-16
Reset
Reset
SPR TBU: 269 read/285 write
SPR 22
W
W
R
R
34–35 WRS Watchdog timer reset status. Functions as write-one-to-clear. Defined at reset (value = 00). Set to
38–63
Bits
32
33
36
37
TBL: 268 read/284 write
32
32
Name
ENW Enable next watchdog time. Functions as write-one-to-clear.
WIS
DIS
FIS
—
Time Base Registers
Decrementer Register
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0 Action on next watchdog timer time-out is to set TSR[ENW]
1 Action on next watchdog timer time-out is governed by TSR[WIS]
When a watchdog timer time-out occurs while WIS = 0 and the next watchdog time-out is enabled
(ENW = 1), a watchdog timer exception is generated and logged by setting WIS. This is referred to as
a watchdog timer first time out. A watchdog timer interrupt occurs if enabled by TCR[WIE] and
MSR[CE]. To avoid another watchdog timer interrupt once MSR[CE] is reenabled, (assuming
TCR[WIE] is not cleared instead), the interrupt handler must reset TSR[WIS].
Watchdog timer interrupt status. Functions as write-one-to-clear.
0 A watchdog timer event has not occurred.
1 A watchdog timer event occurred. When MSR[CE] = 1 and TCR[WIE] = 1, a watchdog timer
See the description of ENW for more information about how WIS is used.
TCR[WRC] when a reset is caused by the watchdog timer.
Decrementer interrupt status. Functions as write-one-to-clear.
0 A decrementer event has not occurred.
1 A decrementer event occurred. When MSR[EE] = TCR[DIE] = 1, a decrementer interrupt is taken.
Fixed-interval timer interrupt status. Functions as write-one-to-clear.
0 A fixed-interval timer event has not occurred.
1 A fixed-interval timer event occurred. When MSR[EE] = 1 and TCR[FIE] = 1, a fixed-interval timer
Reserved, should be cleared.
interrupt is taken.
interrupt is taken.
Figure 6-12. Time Base Upper/Lower Registers (TBU/TBL)
TBU
Figure 6-13. Decrementer Register (DEC)
Table 6-10. TSR Field Descriptions
Decrementer value
All zeros
All zeros
63 32
Description
Access: User read/Supervisor write
TBL
Access: Supervisor read/write
Freescale Semiconductor
63
63
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