MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 7

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
4.1
4.2
4.2.1
4.2.2
4.3
4.3.1
4.3.1.1
4.3.1.1.1
4.3.1.1.2
4.3.1.2
4.3.1.2.1
4.3.1.2.2
4.3.1.3
4.3.1.3.1
4.3.2
4.4
4.4.1
4.4.1.1
4.4.1.2
4.4.2
4.4.3
4.4.3.1
4.4.3.2
4.4.3.3
4.4.3.4
4.4.3.5
4.4.3.6
4.4.3.7
4.4.3.8
4.4.3.9
4.4.3.10
4.4.3.11
4.4.3.12
4.4.3.13
4.4.3.14
4.4.3.15
4.4.3.16
4.4.3.17
Freescale Semiconductor
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Overview.......................................................................................................................... 4-1
External Signal Descriptions ........................................................................................... 4-1
Memory Map/Register Definition ................................................................................... 4-4
Functional Description..................................................................................................... 4-8
System Control Signals................................................................................................ 4-2
Clock Signals ............................................................................................................... 4-3
Local Configuration Control........................................................................................ 4-4
Boot Sequencer ............................................................................................................ 4-8
Reset Operations .......................................................................................................... 4-8
Power-On Reset Sequence........................................................................................... 4-9
Power-On Reset Configuration.................................................................................. 4-10
Accessing Configuration, Control, and Status Registers......................................... 4-4
Accessing Alternate Configuration Space ............................................................... 4-6
Boot Page Translation.............................................................................................. 4-7
Soft Reset................................................................................................................. 4-8
Hard Reset ............................................................................................................... 4-8
System PLL Ratio.................................................................................................. 4-11
e500 Core PLL Ratio ............................................................................................. 4-12
SEC Frequency Ratio Configuration ..................................................................... 4-13
Boot ROM Location .............................................................................................. 4-13
Host/Agent Configuration ..................................................................................... 4-14
I/O Port Selection .................................................................................................. 4-15
CPU Boot Configuration ....................................................................................... 4-16
Boot Sequencer Configuration .............................................................................. 4-17
DDR SDRAM Type............................................................................................... 4-18
eTSEC1 Serial GMII and eTSEC3 Serial GMII.................................................... 4-18
eTSEC1 Width ....................................................................................................... 4-19
eTSEC3 Width ....................................................................................................... 4-19
eTSEC1 Protocol ................................................................................................... 4-19
eTSEC3 Protocol ................................................................................................... 4-20
SGMII SerDes Reference Clock Configuration .................................................... 4-20
PCI Clock Selection............................................................................................... 4-21
PCI Speed Configuration ....................................................................................... 4-21
Updating CCSRBAR ........................................................................................... 4-4
Configuration, Control, and Status Base Address Register (CCSRBAR)........... 4-5
Alternate Configuration Base Address Register (ALTCBAR)............................ 4-6
Alternate Configuration Attribute Register (ALTCAR)...................................... 4-6
Boot Page Translation Register (BPTR).............................................................. 4-7
Reset, Clocking, and Initialization
Contents
Chapter 4
Title
Number
Page
vii