MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 1245
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
The following table,
different interfaces supported by the watchpoint monitor.
Freescale Semiconductor
13–15 Reserved
20–24 Reserved
26–31 Reserved
Bit
10
11
12
16
17
18
19
25
0
1
2
3
4
5
6
7
8
9
Write with local processor snoop
Write with no local processor snoop
Write with allocate(L2 stashing)
Write with allocate and lock (L2 stashing with locking) Write with allocate and lock
Reserved
Reserved
Reserved
Reserved
Read with local processor snoop
Read with no local processor snoop
Read with unlock
Reserved
Reserved
ATOMIC clear
ATOMIC set
ATOMIC decrement
ATOMIC increment
Address only transaction
e500 Coherency Module Dispatch
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table
21-12, defines the transactions associated with each transaction mask bit for the
Table 21-12. Transaction Types By Interface
Description
ATOMIC decrement
ATOMIC increment
Write with allocate
Read with unlock
DDR Controller
ATOMIC clear
ATOMIC set
Write
Read
—
—
—
—
—
—
—
—
—
—
—
—
Debug Features and Watchpoint Facility
PCI Outbound
Memory Read
Memory write
I/O Read
Request
I/O write
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Non-posted Write
Read Response
PCI Express
Posted Write
Transaction
Outbound
Read
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
21-15
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