MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 475
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
11.5
This section describes some programming guidelines recommended for the I
a recommended flowchart for I
The I
software must swap the bytes appropriately. This appropriate byte swapping is needed as I
byte registers. Also, an msync assembly instruction must be executed after each I
access to guarantee in-order execution.
The I
malfunctioning device may hold the bus captive. A good programming practice is for software to rely on
a watchdog timer to help recover from I
when the status bits returned after an interrupt are not consistent with what was expected due to illegal I
bus protocol behavior.
11.5.1
A hard reset initializes all the I
initializes the I
Freescale Semiconductor
1. All I
2. Update I2CFDR[FDR] and select the required division ratio to obtain the SCL frequency from the
3. Update I2CADR to define the slave address for this device.
2
2
C registers in this chapter are shown in big-endian format. If the system is in little-endian mode,
C controller does not guarantee its recovery from all illegal I
CCB (platform) clock. Note that the platform frequency must first be divided by two; see
Section 11.3.1.2, “I
Initialization/Application Information
2
C registers must be located in a cache-inhibited page.
Initialization Sequence
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
2
C unit:
ACS
0
0
0
2
C Frequency Divider Register
0
0
0
Figure 11-10. EEPROM Contents (continued)
2
2
C registers to their default states. The following initialization sequence
C interrupt service routines.
BYTE_EN
0
0
0
ADDR[10–17]
DATA[16–23]
DATA[24–31]
CRC[16–23]
CRC[24–31]
DATA[8–15]
ADDR[2–9]
CRC[8–15]
DATA[0–7]
CRC[0–7]
2
C bus hangs. The recovery routine should also handle the case
0
0
0
0
0
0
1
0
0
0
ADDR[0–1]
0
0
0
(I2CFDR),” for more details.
0
0
0
Cyclic Redundancy
Preload Command
Last Configuration
2
End Command
C bus activity. In addition, a
Check
2
C interface.
2
C register read/write
2
Figure 11-11
C registers are
I
2
C Interfaces
11-21
2
is
C
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