MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 11
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
Paragraph
Number
6.12.5
6.12.5.1
6.12.5.2
6.12.5.3
6.12.5.4
6.12.5.5
6.12.5.6
6.12.5.7
6.13
6.13.1
6.13.1.1
6.13.1.2
6.13.1.3
6.13.2
6.13.3
6.13.4
6.14
6.14.1
6.15
6.15.1
6.15.2
6.15.3
6.15.4
7.1
7.1.1
7.2
7.2.1
7.2.2
7.2.3
7.3
7.3.1
7.3.1.1
7.3.1.2
7.3.1.2.1
7.3.1.2.2
Freescale Semiconductor
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Debug Registers ............................................................................................................. 6-39
Signal Processing and Embedded Floating-Point Status
Performance Monitor Registers (PMRs) ....................................................................... 6-48
L2 Cache Overview ......................................................................................................... 7-1
L2 Cache and SRAM Organization ................................................................................. 7-4
Memory Map/Register Definition ................................................................................... 7-8
MMU Assist Registers............................................................................................... 6-35
Debug Control Registers (DBCR0–DBCR2) ............................................................ 6-39
Debug Status Register (DBSR).................................................................................. 6-43
Instruction Address Compare Registers (IAC1–IAC2) ............................................. 6-45
Data Address Compare Registers (DAC1–DAC2).................................................... 6-45
and Control Register (SPEFSCR).............................................................................. 6-45
Accumulator (ACC)................................................................................................... 6-47
Global Control Register 0 (PMGC0, UPMGC0)....................................................... 6-49
Local Control A Registers (PMLCa0–PMLCa3, UPMLCa0–UPMLCa3) ............... 6-50
Local Control B Registers (PMLCb0–PMLCb3, UPMLCb0–UPMLCb3) .............. 6-51
Performance Monitor Counter Registers (PMC0–PMC3, UPMC0–UPMC3).......... 6-52
L2 Cache and SRAM Features .................................................................................... 7-2
Accessing the On-Chip Array as an L2 Cache ............................................................ 7-5
Accessing the On-Chip Array as an SRAM ................................................................ 7-5
Connection of the On-Chip Memory to the System .................................................... 7-7
L2/SRAM Register Descriptions ............................................................................... 7-10
MAS Register 0 (MAS0) ....................................................................................... 6-35
MAS Register 1 (MAS1) ....................................................................................... 6-35
MAS Register 2 (MAS2) ....................................................................................... 6-36
MAS Register 3 (MAS3) ....................................................................................... 6-37
MAS Register 4 (MAS4) ....................................................................................... 6-38
MAS Register 6 (MAS6) ....................................................................................... 6-38
MAS Register 7 (MAS7) ....................................................................................... 6-39
Debug Control Register 0 (DBCR0)...................................................................... 6-39
Debug Control Register 1 (DBCR1)...................................................................... 6-41
Debug Control Register 2 (DBCR2)...................................................................... 6-42
L2 Control Register (L2CTL)................................................................................ 7-10
L2 Cache External Write Registers ....................................................................... 7-13
L2 Cache External Write Address Registers 0–3 (L2CEWARn) ...................... 7-13
L2 Cache External Write Address Registers Extended Address 0–3
(L2CEWAREAn)........................................................................................... 7-14
L2 Look-Aside Cache/SRAM
Contents
Chapter 7
Title
Number
Page
xi
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