MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 295

Manufacturer Part Number

BOARD DEVELOPMENT SYSTEM 8544

Manufacturer

Freescale Semiconductor

PowerQUICC III™r

Processor To Be Evaluated

Data Bus Width

Interface Type

Ethernet, I2C

Operating Supply Voltage

- 0.3 V to + 1.1 V

Leaded Process Compatible

Peak Reflow Compatible (260 C)

Rohs Compliant

For Use With/related Products

For Use With

PPC8544EVTANG - EVAL MPC8544 783FCPBGA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Data from an I/O master can be allocated into the L2 cache while simultaneously being written to memory.

External (stashed) writes can be performed from any I/O master. For example:

Freescale Semiconductor

Offset 0x2_0E54

Offset 0x2_0E58

PCI/PCI-Express

L2CTHRESH L2 cache threshold. Threshold value for the number of ECC single-bit errors that are detected before

L2CCOUNT L2 count. Counts ECC single-bit errors detected. If L2CCOUNT equals the ECC single-bit error

External Writes to the L2 Cache (Cache Stashing)

describes L2ERRADDRL[L2ADDRL].

describes L2ERRCTL fields.

shows the L2 error address capture register low (L2ERRADDRL).

shows the L2 error control register (L2ERRCTL).

MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1

Figure 7-24. L2 Error Address Capture Register (L2ERRADDRL)

reporting an error condition.

trigger threshold, an error is reported if single-bit error reporting is enabled.

Figure 7-25. L2 Error Control Register (L2ERRCTL)

Table 7-21. L2ERRADDRL Field Description

Table 7-22. L2ERRCTL Field Descriptions

L2 address bits 0–3 corresponding to detected error

L2 Look-Aside Cache/SRAM

Access: Read/Write

Access: Read Only