MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 289
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
Table 7-11
Figure 7-15
Table 7-12
Freescale Semiconductor
Offset 0x2_0E08
Reset
16–21
24–31
0–31
0–14
Bits
Bits
15
22
23
W
R
0
EIMASKLO Error injection mask/low word. A set bit corresponding to a data path bit causes that bit on the data path
ECCERRIM Error injection mask for the ECC bits. A set bit corresponding to an ECC bit causes that bit to be
DERRIEN
TERRIEN
ECCMB
describes L2ERRINJLO[EIMASKLO].
Name
describes L2ERRINJCTL fields.
Name
shows the L2 error injection mask control register (L2ERRINJCTL).
—
—
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure 7-15. L2 Error Injection Mask Control Register (L2ERRINJCTL)
to be inverted on SRAM writes if L2ERRINJCTL[DERRIEN] = 1.
Reserved
0 No tag errors are injected.
1 All subsequent entries written to the L2 tag array have the parity bit inverted.
Reserved
0 ECC byte mirroring is disabled
1 The most significant data path byte is mirrored onto the ECC byte if DERRIEN = 1.
0 No data errors are injected.
1 Subsequent entries written to the L2 data array have data or ECC bits inverted as specified in the
Note: if both ECC mirror byte and data error injection are enabled, ECC mask error injection is
performed on the mirrored ECC.
inverted on SRAM writes if DERRIEN = 1.
L2 tag array error injection enable
ECC mirror byte enable.
L2 data array error injection enable:
—
data and ECC error injection masks and/or data path byte mirrored onto ECC as specified by ECC
mirror byte enable.
Table 7-12. L2ERRINJCTL Field Descriptions
Table 7-11. L2ERRINJLO Field Description
14
TERRIEN
15
16
All zeros
—
Description
Description
21
ECCMB
22
DERRIEN
23
L2 Look-Aside Cache/SRAM
24
Access: Read/Write
ECCERRIM
7-19
31
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