MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 605

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.3.1.4
The UIER gives the user the ability to mask specific UART interrupts to the programmable interrupt
controller (PIC).
Figure 13-6
Table 13-9
13.3.1.5
The UIIRs indicate when an interrupt is pending from the corresponding UART and what type of interrupt
is active. They also indicate if the FIFOs are enabled.
The DUART prioritizes interrupts into four levels and records these in the corresponding UIIR. The four
levels of interrupt conditions in order of priority are:
Freescale Semiconductor
Bits
0–3
4
5
6
7
1. Receiver line status
2. Received data ready/character time-out
Offset 0x501, 0x601
Reset
ETHREI Enable transmitter holding register empty interrupt.
ERDAI
ERLSI
Name
EMSI
W
R
—
describes the fields of UIER.
shows the bits in the UIER.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Interrupt Enable Register (UIER) (ULCR[DLAB] = 0)
Interrupt ID Registers (UIIR0, UIIR1) (ULCR[DLAB] = 0)
Reserved.
Enable modem status interrupt.
0 Mask interrupts caused by UMSR[DCTS] being set
1 Enable and assert interrupts when the clear-to-send bit in the UART modem status register (UMSR)
0 Mask interrupts when ULSR’s overrun, parity error, framing error or break interrupt bits are set
1 Enable and assert interrupts when ULSR’s overrun, parity error, framing error or break interrupt bits are
0 Mask interrupt when ULSR[THRE] is set
1 Enable and assert interrupts when ULSR[THRE] is set
0 Mask interrupt when new receive data is available or receive data time out has occurred
1 Enable and assert interrupts when a new data character is received from the external device and/or a
Enable receiver line status interrupt.
Enable received data available interrupt.
0
changes state
set
time-out interrupt occurs in the FIFO mode
Figure 13-6. Interrupt Enable Register (UIER)
—
Table 13-9. UIER Field Descriptions
3
All zeros
Description
EMSI
4
ERLSI
5
ETHREI
Access: Read/Write
6
ERDAI
7
DUART
13-9