MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 1255
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
Table 21-25
21.4
The debug features on the MPC8544E use the LBC interfaces, and the DDR SDRAM interface.
21.4.1
Debug information that is common to all the interfaces is the source ID (SID). The transaction source ID
provides enough information to determine which block or port originated a transaction including the
distinction between instruction and data fetches from the processor core.
interpretation for the 5-bit SID field. Note that the table also includes ports that are only slaves, such as
local memory. These ports are always targets. As such, the value shown represents a target ID (TID) and
not a source ID. For ports that can function in both capacities, the value indicates source ID when
mastering transactions, and target ID when responding as slave. The TID field is only meaningful when
one of the following participates in the transaction:
Freescale Semiconductor
8–31
Bits
0–4
5–7
•
•
•
(Hex)
Value
The e500 coherency module (ECM) dispatch bus
The watchpoint monitor (WMCR1[IFSEL] = 000)
The trace buffer (TBCR1[IFSEL] = 000)
00
01
02
03
04
05
Name
SEL
Functional Description
—
—
Source and Target ID
describes the TOSR fields.
PCI
PCI Express 2
PCI Express 1
PCI Express 3
Local bus controller
Reserved
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
Select. Selects the source for TRIG_OUT
000 READY signal. Multiplexed with TRIG_OUT. Basic device state indicator. READY asserts whenever the
001 Selects the watchpoint monitor hit indication
010 Selects the trace buffer hit indication
011 Selects the performance monitor overflow indication
Reserved
device is not in reset or not asleep. See
about the reset sequence, and
management states.
Source (or Target) Port
Table 21-26. Source and Target ID Values
Table 21-25. TOSR Field Descriptions
Chapter 19, “Global Utilities,”
(Hex)
Value
Chapter 4, “Reset, Clocking, and Initialization,”
14
15
10
11
12
13
Description
Local processor (instruction fetch)
Local processor (data fetch)
Reserved
Reserved
Reserved
DMA
Source (or Target) Port
for more information about power
Table 21-26
Debug Features and Watchpoint Facility
shows the values and
for more details
21-25
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