SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 1035
SAM9G45
Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G45.pdf
(10 pages)
5.SAM9G45.pdf
(55 pages)
6.SAM9G45.pdf
(1196 pages)
Specifications of SAM9G45
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G45 PDF datasheet #4
- SAM9G45 PDF datasheet #5
- SAM9G45 PDF datasheet #6
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43.7.3
Figure 43-4. Logical Channel Assignment
6438G–ATARM–19-Apr-11
(Controller Output)
(Codec output)
AC97 Controller Channel Organization
AC97RX
AC97FS
AC97TX
Slot #
AC97C_ICA = 0x0000_0009
AC97C_OCA = 0x0000_0209
TAG
TAG
0
The AC97 Controller features a Codec channel and 2 logical channels: Channel A, Channel B.
The Codec channel controls AC97 Codec registers, it enables write and read configuration val-
ues in order to bring the AC97 Codec to an operating state. The Codec channel always runs slot
1 and slot 2 exclusively, in both input and output directions.
Channel A, Channel B transfer data to/from AC97 codec. All audio samples and modem data
must transit by these 2 channels. However, Channels A and B are connected to PDC channels
thus making it suitable for audio streaming applications.
Each slot of the input or the output frame that belongs to this range [3 to 12] can be operated by
Channel A or Channel B . The slot to channel assignment is configured by two registers:
The AC97 Controller Input Channel Assignment Register (AC97C_ICA) configures the input slot
to channel assignment. The AC97 Controller Output Channel Assignment Register
(AC97C_OCA) configures the output slot to channel assignment.
A slot can be left unassigned to a channel by the AC97 Controller. Slots 0, 1,and 2 cannot be
assigned to Channel A or to Channel Bthrough the AC97C_OCA and AC97C_ICA Registers.
The width of sample data, that transit via the Channel varies and can take one of these values;
10, 16, 18 or 20 bits.
STATUS
• AC97 Controller Input Channel Assignment Register (AC97C_ICA)
• AC97 Controller Output Channel Assignment Register (AC97C_OCA)
ADDR
ADDR
CMD
Codec Channel
1
Codec Channel
STATUS
DATA
DATA
CMD
2
3
L Front
LEFT
PCM
PCM
Channel A
Channel A
R Front
RIGHT
4
PCM
PCM
LINE 1
LINE 1
5
DAC
DAC
6
Center
PCM
PCM
MIC
L SURR
RSVED
7
PCM
R SURR
RSVED
PCM
8
RSVED
PCM
9
LFE
LINE 2
LINE 2
10
ADC
DAC
11
SAM9G45
HSET
HSET
ADC
DAC
STATUS
12
CTRL
IO
IO
1035
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