SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 253

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Table 22-4.
Note:
22.5.2
Table 22-6.
Table 22-7.
Table 22-8.
Notes:
6438G–ATARM–19-Apr-11
27
27
27
27
Bk[1:0]
Bk[1:0]
26
26
26
26
Bk[1:0]
Bk[1:0]
Bk[1:0]
1. SDR-SDRAM devices with eight columns in 16-bit mode are not supported.
1. M[1:0] is the byte address inside a 32-bit word.
2. Bk[1] = BA1, Bk[0] = BA0
25
25
25
25
SDR-SDRAM Address Mapping for 32-bit Memory Data Bus Width
Bk[1:0]
Bk[1:0]
Bk[1:0]
Bk[1:0]
24
24
24
24
Linear Mapping for SDRAM Configuration: 16K Rows, 512/1024/2048 Columns
SDR-SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
SDR-SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
SDR-SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
Bk[1:0]
Bk[1:0]
Bk[1:0]
23
23
23
23
Bk[1:0]
Bk[1:0]
22
22
22
22
Bk[1:0]
21
21
21
21
20
20
20
20
Row[12:0]
Row[13:0]
Row[11:0]
19
19
19
19
Row[10:0]
Row[12:0]
Row[13:0]
Row[11:0]
18
18
18
18
Row[10:0]
Row[12:0]
Row[13:0]
Row[11:0]
17
17
17
17
Row[10:0]
Row[12:0]
Row[11:0]
16
16
16
16
Row[10:0]
15
15
15
15
CPU Address Line
CPU Address Line
CPU Address Line
CPU Address Line
14
14
14
14
13
13
13
13
12
12
12
12
11
11
11
11
10
10
10
10
9
9
9
9
8
8
Column[10:0]
8
Column[10:0]
8
Column[10:0]
Column[9:0]
Column[9:0]
Column[9:0]
7
7
7
7
Column[10:0]
Column[8:0]
Column[8:0]
Column[8:0]
Column[9:0]
Column[7:0]
Column[7:0]
Column[7:0]
6
6
6
6
Column[8:0]
5
5
5
5
4
4
4
4
SAM9G45
3
3
3
3
2
2
2
2
1
1
1
1
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M0
M0
M0
253
0
0
0
0