SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 136

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

19.5
19.5.1
19.5.1.1
136
Arbitration
SAM9G45
Arbitration Scheduling
Undefined Length Burst Arbitration
This configuration provides no benefit on access latency or bandwidth when reaching maximum
slave bus throughput whatever is the number of requesting masters.
The Bus Matrix provides an arbitration mechanism that reduces latency when conflict cases
occur, i.e. when two or more masters try to access the same slave at the same time. One arbiter
per AHB slave is provided, thus arbitrating each slave differently.
The Bus Matrix provides the user with the possibility of choosing between 2 arbitration types or
mixing them for each slave:
The resulting algorithm may be complemented by selecting a default master configuration for
each slave.
When a re-arbitration must be done, specific conditions apply. See
Scheduling” on page
Each arbiter has the ability to arbitrate between two or more different master requests. In order
to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitra-
tion may only take place during the following cycles:
In order to optimize AHB burst lengths and arbitration, it may be interesting to set a maximum for
undefined length bursts (INCR). The Bus Matrix provides specific logic in order to re-arbitrate
before the end of the INCR transfer. A predicted end of burst is used as a defined length burst
transfer and can be selected from among the following Undefined Length Burst Type (ULBT)
possibilities:
1. Round-Robin Arbitration (default)
2. Fixed Priority Arbitration
1. Idle Cycles: When a slave is not connected to any master or is connected to a master
2. Single Cycles: When a slave is currently doing a single access.
3. End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For
4. Slot Cycle Limit: When the slot cycle counter has reached the limit value indicating that
1. Unlimited: No predicted end of burst is generated and therefore INCR burst transfer will
2. 1-beat bursts: Predicted end of burst is generated at each single transfer inside the
3. 4-beat bursts: Predicted end of burst is generated at the end of each 4-beat boundary
which is not currently accessing it.
defined length burst, predicted end of burst matches the size of the transfer but is man-
aged differently for undefined length burst. See
page 136
the current master access is too long and must be broken. See
tration” on page 137
not be broken by this way, but will be able to complete unless broken at the Slot Cycle
Limit. This is normally the default and should be let as is in order to be able to allow full
1 Kilobyte AHB intra-boundary 256-beat word bursts performed by some ATMEL AHB
masters.
INCR transfer.
inside INCR transfer.
136.
“Undefined Length Burst Arbitration” on
Section 19.5.1 “Arbitration
“Slot Cycle Limit Arbi-
6438G–ATARM–19-Apr-11