SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 921

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SAM9G45

Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G45

Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
6438G–ATARM–19-Apr-11
Figure 40-4. Touch Screen Pen Detect
The Touch Screen Pen Detect can be used to generate a TSADCC interrupt to wake up the sys-
tem or it can be programmed to trig a conversion, so that a position can be measured as soon as
a contact is detected if the TSADCC is programmed for an operating mode involving the Touch
Screen.
The Pen Detect generates two types of status, reported in the
Both bits are automatically cleared as soon as the Status Register TSADCC_SR is read, and
can generate an interrupt by writing accordingly the
• the bit PENCNT is set as soon as a current flows for a time over the debouncing time as
• the bit NOCNT is set as soon as no current flows for a time over the debouncing time as
defined by PENDBC and remains set until TSADCC_SR is read.
defined by PENDBC and remains set until TSADCC_SR is read.
X
Y
X
Y
M
M
P
P
VDDANA
VDDANA
GND
GND
GND
“TSADCC Interrupt Enable
To the ADC
“TSADCC Status
Debouncer
PENDBC
SAM9G45
Pen Interrupt
Register”.
Register”:
921

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