SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 138

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

19.5.2.1
19.5.2.2
138
SAM9G45
Fixed Priority Arbitration
Round-Robin Arbitration
For each slave, each master x is assigned to one of the slave priority pools through the Priority
Registers for Slaves (MxPR fields of MATRIX_PRAS and MATRIX_PRBS). When evaluating
masters requests, this programmed priority level always takes precedence.
After reset, all the masters are belonging to the lowest priority pool (MxPR = 0) and so are
granted bus access in a true Round-Robin fashion.
The highest priority pool must be specifically reserved for masters requiring very low access
latency. If more than one master belong to this pool, these will be granted bus access in a
biased Round-Robin fashion which allow tight and deterministic maximum access latency from
AHB bus request. In fact, at worst, any currently high priority master request will be granted after
the current bus master access is ended and the other high priority pool masters, if any, have
been granted once each.
The lowest priority pool shares the remaining bus bandwidth between AHB Masters.
Intermediate priority pools allow fine priority tuning. Typically, a moderately latency critical mas-
ter or a bandwidth only critical master will use such a priority level. The higher the priority level
(MxPR value), the higher the master priority.
All combination of MxPR values are allowed for all masters and slaves. For example some mas-
ters might be assigned to the highest priority pool (round-robin) and the remaining masters to
the lowest priority pool (round-robin), with no master for intermediate fix priority levels.
If more than one master is requesting the slave bus, whatever are the respective masters priori-
ties, no master will be granted the slave bus for two consecutive runs. A master can only get
back to back grants as long as it is the only requesting master.
This arbitration algorithm is the first and only applied between masters from distinct priority
pools. It is also used inside priority pools other than the highest and lowest ones (intermediate
priority pools).
It allows the Bus Matrix arbiters to dispatch the requests from different masters to the same
slave by using the fixed priority defined by the user in the MxPR field for each master inside the
MATRIX_PRAS and MATRIX_PRBS Priority Registers. If two or more master requests are
active at the same time, the master with the highest priority number MxPR is serviced first.
Inside intermediate priority pools, if two or more master requests with the same priority are
active at the same time, the master with the highest number is serviced first.
This algorithm is only used inside the highest and lowest priority pools. It allows the Bus Matrix
arbiters to dispatch the requests from different masters to the same slave in a fair way. If two or
more master requests are active at the same time inside the priority pool, they are serviced in a
round-robin increasing master number order.
6438G–ATARM–19-Apr-11