SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 884

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SAM9G45

Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G45

Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
39.5.1
Register Name:
Access Type:
Reset Value:
• HSYNC_POL: Horizontal Synchronization Polarity
0: HSYNC active high.
1: HSYNC active low.
• VSYNC_POL: Vertical Synchronization Polarity
0: VSYNC active high.
1: VSYNC active low.
• PIXCLK_POL: Pixel Clock Polarity
0: Data is sampled on rising edge of pixel clock.
1: Data is sampled on falling edge of pixel clock.
• EMB_SYNC: Embedded Synchronization
0: Synchronization by HSYNC, VSYNC.
1: Synchronization by embedded synchronization sequence SAV/EAV.
• CRC_SYNC: Embedded Synchronization Correction
0: No CRC correction is performed on embedded synchronization.
1: CRC correction is performed. if the correction is not possible, the current frame is discarded and the CRC_ERR is set in
the status register.
• FRATE: Frame Rate [0..7]
0: All the frames are captured, else one frame every FRATE+1 is captured.
• DISCR: Disable Codec Request
0 = Codec datapath DMA interface requires a request to restart.
1 = Codec datapath DMA automatically restarts.
884
CRC_SYNC
31
23
15
7
SAM9G45
ISI Configuration 1 Register
EMB_SYNC
30
22
14
6
ISI_CFG1
Read-write
0x00000000
THMASK
29
21
13
5
PIXCLK_POL
FULL
28
20
12
4
SFD
SLD
VSYNC_POL
DISCR
27
19
11
3
HSYNC_POL
26
18
10
2
FRATE
25
17
9
1
6438G–ATARM–19-Apr-11
24
16
8
0

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