SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 317

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

25.12.10 PMC Clock Generator PLLA Register
Register Name:CKGR_PLLAR
Address:
Access Type:Read/Write
Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC.
Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
• DIVA: Divider A
• PLLACOUNT: PLLA Counter
Specifies the number of slow clock cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.
• OUTA: PLLA Clock Frequency Range
To optimize clock performance, this field must be programmed as specified in “PLL Characteristics” in the Electrical Char-
acteristics section of the product datasheet.
• MULA: PLLA Multiplier
0 = The PLLA is deactivated.
1 up to 254 = The PLLA Clock frequency is the PLLA input frequency multiplied by MULA+ 1.
6438G–ATARM–19-Apr-11
DIVA
0
1
2 - 255
31
23
15
–
7
OUTA
0xFFFFFC28
30
22
14
–
6
29
21
13
1
5
Divider Selected
Divider output is 0
Divider is bypassed
Divider output is the selected clock divided by DIVA.
28
20
12
–
4
MULA
DIVA
27
19
11
–
3
PLLACOUNT
26
18
10
–
2
25
17
–
9
1
SAM9G45
24
16
–
8
0
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