SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 869

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

• END_TR_EN: End of Transfer Enable (Control)
Used for OUT transfers only.
0 = USB end of transfer is ignored.
1 = UDPHS device can put an end to the current buffer transfer.
When set, a BULK or INTERRUPT short packet or the last packet of an ISOCHRONOUS (micro) frame (DATAX) will close
the current buffer and the UDPHS_DMASTATUSx register END_TR_ST flag will be raised.
This is intended for UDPHS non-prenegotiated end of transfer (BULK or INTERRUPT) or ISOCHRONOUS microframe
data buffer closure.
• END_B_EN: End of Buffer Enable (Control)
0 = DMA Buffer End has no impact on USB packet transfer.
1 = endpoint can validate the packet (according to the values programmed in the UDPHS_EPTCTLx register AUTO_VALID
and SHRT_PCKT fields) at DMA Buffer End, i.e. when the UDPHS_DMASTATUS register BUFF_COUNT reaches 0.
This is mainly for short packet IN validation initiated by the DMA reaching end of buffer, but could be used for OUT packet
truncation (discarding of unwanted packet data) at the end of DMA buffer.
• END_TR_IT: End of Transfer Interrupt Enable
0 = UDPHS device initiated buffer transfer completion will not trigger any interrupt at UDPHS_STATUSx/END_TR_ST
rising.
1 = an interrupt is sent after the buffer transfer is complete, if the UDPHS device has ended the buffer transfer.
Use when the receive size is unknown.
• END_BUFFIT: End of Buffer Interrupt Enable
0 = UDPHS_DMA_STATUSx/END_BF_ST rising will not trigger any interrupt.
1 = an interrupt is generated when the UDPHS_DMASTATUSx register BUFF_COUNT reaches zero.
• DESC_LD_IT: Descriptor Loaded Interrupt Enable
0 = UDPHS_DMASTATUSx/DESC_LDST rising will not trigger any interrupt.
1 = an interrupt is generated when a descriptor has been loaded from the bus.
• BURST_LCK: Burst Lock Enable
0 = the DMA never locks bus access.
1 = USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of
fly-by AHB burst duration.
• BUFF_LENGTH: Buffer Byte Length (Write-only)
This field determines the number of bytes to be transferred until end of buffer. The maximum channel transfer size (64
KBytes) is reached when this field is 0 (default value). If the transfer size is unknown, this field should be set to 0, but the
transfer end may occur earlier under UDPHS device control.
When this field is written, The UDPHS_DMASTATUSx register BUFF_COUNT field is updated with the write value.
Note:
Note:
6438G–ATARM–19-Apr-11
Bits [31:2] are only writable when issuing a channel Control Command other than “Stop Now”.
For reliability it is highly recommended to wait for both UDPHS_DMASTATUSx register CHAN_ACT and CHAN_ENB flags are
at 0, thus ensuring the channel has been stopped before issuing a command other than “Stop Now”.
SAM9G45
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