SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 16
SAM9G45
Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G45.pdf
(10 pages)
5.SAM9G45.pdf
(55 pages)
6.SAM9G45.pdf
(1196 pages)
Specifications of SAM9G45
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G45 PDF datasheet #4
- SAM9G45 PDF datasheet #5
- SAM9G45 PDF datasheet #6
- Current page: 16 of 1196
- Download datasheet (20Mb)
6.1
6.2
6.2.1
16
Memory Mapping
Embedded Memories
SAM9G45
Internal SRAM
A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of
the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional
features.
Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. The banks 1 to
6 are directed to the EBI that associates these banks to the external chip selects NCS0 to
NCS5.
The bank 7 is directed to the DDRSDRC0 that associates this bank to DDR_NCS chip select
and so dedicated to the 4-port DDR2/ LPDDR controller.
The bank 0 is reserved for the addressing of the internal memories, and a second level of
decoding provides 1 Mbyte of internal memory area. The bank 15 is reserved for the peripherals
and provides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master
requesting such an access.
The SAM9G45 product embeds a total of 64Kbytes high-speed SRAM split in 4 blocks of 16
KBytes connected to one slave of the matrix. After reset and until the Remap Command is per-
formed, the four SRAM blocks are contiguous and only accessible at address 0x00300000. After
Remap, the SRAM also becomes available at address 0x0.
Figure 6-2.
The SAM9G45 device embeds two memory features. The processor Tightly Coupled Memory
Interface (TCM) that allows the processor to access the memory up to processor speed (PCK)
and the interface on the AHB side allowing masters to access the memory at AHB speed (MCK).
A wait state is necessary to access the TCM at 400 MHz. Setting the bit NWS_TCM in the bus
Matrix TCM Configuration Register of the matrix inserts a wait state on the ITCM and DTCM
accesses.
0x00300000
Internal SRAM Reset
RAM
64K
Remap
RAM
64K
6438G–ATARM–19-Apr-11
0x00000000
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