SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 228

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

22.2
Figure 22-1.
228
AHB Slave Interface 0
AHB Slave Interface 1
AHB Slave Interface 2
AHB Slave Interface 3
DDRSDRC Module Diagram
SAM9G45
DDRSDRC Module Diagram
APB
DDRSDRC is partitioned in two blocks (see
• An Interconnect-Matrix that manages concurrent accesses on the AHB bus between four
• A controller that translates AHB requests (Read/Write) in the SDRAM protocol.
AHB masters and integrates an arbiter.
Stage
Stage
Stage
Stage
Input
Input
Input
Input
Interconnect Matrix
Interface APB
Output
Arbiter
Stage
SDRAM Signal Management
Asynchronous Timing
Refresh Management
DDR-SDR Controller
Finite State Machine
Power Management
Memory Controller
Figure
22-1):
Addr, DQM
ras,cas,we
cke
clk/nclk
Data
DQS
6438G–ATARM–19-Apr-11
odt
DDR-SDR
Devices