SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 294

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

24.6.4
24.7
24.7.1
294
Divider and PLLA Block
SAM9G45
Main Oscillator Bypass
Divider and Phase Lock Loop Programming
When the MOSCEN bit and the OSCOUNT are written in CKGR_MOR to enable the main oscil-
lator, the MOSCS bit in PMC_SR (Status Register) is cleared and the counter starts counting
down on the slow clock divided by 8 from the OSCOUNT value. Since the OSCOUNT value is
coded with 8 bits, the maximum startup time is about 62 ms.
When the counter reaches 0, the MOSCS bit is set, indicating that the main clock is valid. Set-
ting the MOSCS bit in PMC_IMR can trigger an interrupt to the processor.
The user can input a clock on the device instead of connecting a crystal. In this case, the user
has to provide the external clock signal on the XIN pin. The input characteristics of the XIN pin
under these conditions are given in the product electrical characteristics section. The program-
mer has to be sure to set the OSCBYPASS bit to 1 and the MOSCEN bit to 0 in the Main OSC
register (CKGR_MOR) for the external clock to operate properly.
The PLLA embeds an input divider to increase the accuracy of the resulting clock signals. How-
ever, the user must respect the PLLA minimum input frequency when programming the divider.
The PLLA embeds also an output divisor by 2.
Figure 24-6
Figure 24-6. Divider and PLLA Block Diagram
The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the
output of the corresponding divider and the PLL output is a continuous signal at level 0. On
reset, each DIV field is set to 0, thus the corresponding PLL input clock is set to 0.
The PLLA allows multiplication of the divider’s outputs. The PLLA clock signal has a frequency
that depends on the respective source signal frequency and on the parameters DIVA and
MULA. The factor applied to the source signal frequency is (MULA + 1)/DIVA. When MULA is
written to 0, the PLLA is disabled and its power consumption is saved. Re-enabling the PLLA
can be performed by writing a value higher than 0 in the MUL field.
Whenever the PLLA is re-enabled or one of its parameters is changed, the LOCKA bit in
PMC_SR is automatically cleared. The values written in the PLLACOUNT field in CKGR_PLLAR
are loaded in the PLLA counter. The PLLA counter then decrements at the speed of the Slow
Clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt
MAINCK
shows the block diagram of the divider and PLLA block.
SLCK
Divider
DIVA
PLLACOUNT
Counter
PLLA
MULA
PLLA
OUTA
LOCKA
PLLADIV2
/1 or /2
Divider
6438G–ATARM–19-Apr-11
PLLACK