SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 1073

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

45. LCD Controller (LCDC)
45.1
45.2
6438G–ATARM–19-Apr-11
Description
Embedded Characteristics
The LCD Controller (LCDC) consists of logic for transferring LCD image data from an external
display buffer to an LCD module with integrated common and segment drivers.
The LCD Controller supports single and double scan monochrome and color passive STN LCD
modules and single scan active TFT LCD modules. On monochrome STN displays, up to 16
gray shades are supported using a time-based dithering algorithm and Frame Rate Control
(FRC) method. This method is also used in color STN displays to generate up to 4096 colors.
The LCD Controller has a display input buffer (FIFO) to allow a flexible connection of the exter-
nal AHB master interface, and a lookup table to allow palletized display configurations.
The LCD Controller is programmable in order to support many different requirements such as
resolutions up to 2048 x 2048; pixel depth (1, 2, 4, 8, 16, 24 bits per pixel); data line width (4, 8,
16 or 24 bits) and interface timing.
The LCD Controller is connected to the ARM Advanced High Performance Bus (AHB) as a mas-
ter for reading pixel data. However, the LCD Controller interfaces with the AHB as a slave in
order to configure its registers.
• Single and Dual scan color and monochrome passive STN LCD panels supported
• Single scan active TFT LCD panels supported.
• 4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported
• Up to 24-bit single scan TFT interfaces supported
• Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays
• 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN
• 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN
• 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT
• Single clock domain architecture
• Resolution supported up to 2048 x 2048
SAM9G45
1073