SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 453

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

30.4.12
6438G–ATARM–19-Apr-11
Programmable I/O Delays
If a write access in a write-protected register is detected, then the WPVS flag in the PIO Write
Protect Status Register (PIO_WPSR) is set and the field WPVSRC indicates in which register
the write access has been attempted.
The WPVS flag is automatically reset after reading the PIO Write Protect Status Register
(PIO_WPSR).
List of the write-protected registers:
The PIO interface consists of a series of signals driven by peripherals or directly by sofware. The
simultaneous switching outputs on these busses may lead to a peak of current in the internal
and external power supply lines.
In order to reduce the peak of current in such cases, additional propagation delays can be
adjusted independently for pad buffers by means of configuration registers, PIO_DELAY.
For each I/O, the additional programmable delays range from 0 to 4 ns (Worst Case PVT). The
delay can differ between IOs supporting this feature. The delay can be modified according to
programming for each I/O. The minimum additional delay that can be programmed on a PAD
supporting this feature is 1/16 of the maximum programmable delay.
Only PADs PC[12], PC[7:2], PA[30:23] and PA[9:2] can be configured.
When programming 0x0 in fields, no delay is added (reset value) and the propagation delay of
the pad buffers is the inherent delay of the pad buffer. When programming 0xF in field, the prop-
agation delay of the corresponding pad is maximal.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
“PIO Enable Register” on page 458
“PIO Disable Register” on page 458
“PIO Output Enable Register” on page 459
“PIO Output Disable Register” on page 460
“PIO Input Filter Enable Register” on page 461
“PIO Input Filter Disable Register” on page 461
“PIO Set Output Data Register” on page 462
“PIO Clear Output Data Register” on page 463
“PIO Multi-driver Enable Register” on page 466
“PIO Multi-driver Disable Register” on page 467
“PIO Pull Up Disable Register” on page 468
“PIO Pull Up Enable Register” on page 468
“PIO Peripheral A Select Register” on page 469
“PIO Peripheral B Select Register” on page 470
“PIO Output Write Enable Register” on page 471
“PIO Output Write Disable Register” on page 471
SAM9G45
453