SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 816

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 38-8. Data IN Transfer for Endpoint with One Bank
Figure 38-9. Data IN Transfer for Endpoint with Two Banks
816
USB Bus
Packets
TX_PK_RDY
Flag
(UDPHS_EPTSTAx)
TX_COMPLT Flag
(UDPHS_EPTSTAx)
FIFO
Content
USB Bus
Packets
Virtual TX_PK_RDY
bank 0
(UDPHS_EPTSTAx)
Virtual TX_PK_RDY
bank 1
(UDPHS_EPTSTAx)
TX_COMPLT
Flag
(UDPHS_EPTSTAx)
FIFO
(DPR)
Bank 0
FIFO
(DPR)
Bank1
SAM9G45
Written by
Microcontroller
Set by Firmware,
Data Payload Written
in FIFO Bank 0
Microcontroller
Load Data IN Bank 0
Token IN
Set by firmware
Prevous Data IN TX
Token IN
Data IN 1
Data IN 1
Cleared by Hardware
switch to next bank
Microcontroller Load Data IN Bank 1
UDPHS Device Send Bank 0
Cleared by hardware
Set by hardware
Written by
Microcontroller
Read by USB Device
ACK
Data IN
Set by Hardware
DPR access by firmware
Microcontroller Loads Data in FIFO
Token IN
Load in progress
Interrupt Pending
Cleared by Hardware
Data Payload Fully Transmitted
ACK
NAK
Interrupt Pending
Set by the firmware
Interrupt Cleared by Firmware
Token IN
Token IN
Cleared by firmware
Microcontroller Load Data IN Bank 0
UDPHS Device Send Bank 1
Written by
Microcontroller
Set by Firmware,
Data Payload Written in FIFO Bank 1
Data is Sent on USB Bus
DPR access by hardware
Read by UDPHS Device
Data IN 2
Payload in FIFO
Data IN 2
Data IN
Set by Hardware
Cleared by hardware
6438G–ATARM–19-Apr-11
Cleared by firmware
Interrupt Pending
ACK
ACK