SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 925

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

40.10.2
6438G–ATARM–19-Apr-11
Touch Screen Mode
If the PDC is enabled, all the converted data are transferred contiguously in the memory buffer.
The bit LOWRES defines which resolution is used, either 8-bit or 10-bit, and thus the width of the
PDC memory buffer.
Writing TSAMOD to “Touch Screen Only Mode” automatically enables the touch screen pins as
analog inputs, and thus disables the digital function of the corresponding pins.
In Touch Screen Mode, the channels 0 to 3 corresponding to the Touch Screen inputs are auto-
matically activated and the bits CH0 to CH3 are automatically set in the
Status
The remaining channels can be either enabled or disabled by the user and their conversions are
performed at the end of each touch screen sequence.
The resolution is forced to 10 bits, regardless of the LOWRES bit setting.
At each trigger, if the bit PRES in
is performed to measure only position.
The resulting buffer is 16 bits wide and its structure stored in memory is:
5. If Channel 1 is enabled, convert Channel 1 and store result in both TSADCC_CDR1
6. If Channel 2 is enabled, convert Channel 2 and store result in both TSADCC_CDR2
7. If Channel 3 is enabled, convert Channel 3 and store result in both TSADCC_CDR3
8. If Channel 4 to Channel 7 are enabled, convert the Channels and store result in the cor-
9. If SLEEP is set, sleep down the ADC cell.
1. If SLEEP is set, wake up the ADC cell and wait for the Startup Time.
2. Close the switches on the inputs X
3. Convert Channel X
4. Close the switches on the inputs X
5. Convert Channel X
6. Close the switches on the inputs X
7. Convert Channel Y
8. Close the switches on the inputs Y
9. Convert Channel Y
10. Close the switches on the inputs Y
11. Convert Channel Y
12. Close the switches on the inputs Y
13. Convert Channel X
14. If Channel 4 to Channel 7 are enabled, convert the Channels and store result in the cor-
15. If SLEEP is set, sleep down the ADC cell.
and TSADCC_LCDR.
and TSADCC_LCDR.
and TSADCC_LCDR.
responding TSADCC_CDRx and TSADCC_LCDR.
result in both TSADCC_CDR0 and TSADCC_LCDR.
result in both TSADCC_CDR1 and TSADCC_LCDR.
result in both TSADCC_CDR2 and TSADCC_LCDR.
result in both TSADCC_CDR3 and TSADCC_LCDR.
responding TSADCC_CDRx and TSADCC_LCDR.
Register”.
P
P
P
P
M
M
, subtract TSADCC_CDR1 from the result and store the subtraction
, subtract TSADCC_CDR1 from the result and store the subtraction
, subtract TSADCC_CDR3 from the result and store the subtraction
, subtract TSADCC_CDR3 from the result and store the subtraction
and store the result in TSADCC_CDR1.
and store the result in TSADCC_CDR3.
“TSADCC Mode Register”
P
P
P
P
P
P
and X
and X
and X
and Y
and Y
and Y
M
M
M
M
M
M
during the Sample and Hold Time.
during the Sample and Hold Time.
during the Sample and Hold Time.
during the Sample and Hold Time.
during the Sample and Hold Time.
during the Sample and Hold Time.
is disabled, the following sequence
“TSADCC Channel
SAM9G45
925