SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 832
SAM9G45
Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G45.pdf
(10 pages)
5.SAM9G45.pdf
(55 pages)
6.SAM9G45.pdf
(1196 pages)
Specifications of SAM9G45
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G45 PDF datasheet #4
- SAM9G45 PDF datasheet #5
- SAM9G45 PDF datasheet #6
- Current page: 832 of 1196
- Download datasheet (20Mb)
38.6.1
Name:
Address:
Access Type:
• DEV_ADDR: UDPHS Address
Read:
This field contains the default address (0) after power-up or UDPHS bus reset.
Write:
This field is written with the value set by a SET_ADDRESS request received by the device firmware.
• FADDR_EN: Function Address Enable
Read:
0 = Device is not in address state.
1 = Device is in address state.
Write:
0 = only the default function address is used (0).
1 = this bit is set by the device firmware after a successful status phase of a SET_ADDRESS transaction. When set, the
only address accepted by the UDPHS controller is the one stored in the UDPHS Address field. It will not be cleared after-
wards by the device firmware. It is cleared by hardware on hardware reset, or when UDPHS bus reset is received (see
above).
• EN_UDPHS: UDPHS Enable
Read:
0 = UDPHS is disabled.
1 = UDPHS is enabled.
Write:
0 = disable and reset the UDPHS controller. Switch the host to UTMI.
1 = enables the UDPHS controller. Switch the host to UTMI.
832
FADDR_EN
31
23
15
–
–
–
7
SAM9G45
UDPHS Control Register
30
22
14
UDPHS_CTRL
0xFFF78000
Read-write
–
–
–
6
29
21
13
–
–
–
5
28
20
12
–
–
–
4
PULLD_DIS
DEV_ADDR
27
19
11
–
–
3
REWAKEUP
26
18
10
–
–
2
DETACH
25
17
–
–
9
1
6438G–ATARM–19-Apr-11
EN_UDPHS
24
16
–
–
8
0
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