SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 982

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

41.6
Table 41-3.
Note:
982
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C+ch_num*(0x28)+(0x0)
0x03C+ch_num*(0x28)+(0x4)
0x03C+ch_num*(0x28)+(0x8)
0x03C+ch_num*(0x28)+(0xC)
0x03C+ch_num*(0x28)+(0x10)
0x03C+ch_num*(0x28)+(0x14)
0x03C+ch_num*(0x28)+(0x18)
0x03C+ch_num*(0x28)+(0x1C)
0x03C+ch_num*(0x28)+(0x20)
0x03C+ch_num*(0x28)+(0x24)
0x064 - 0x140
0x017C- 0x1FC
DMA Controller (DMAC) User Interface
1. The addresses for the DMAC registers shown here are for DMA Channel 0. This sequence of registers is repeated succes-
SAM9G45
sively for each DMA channel located between 0x064 and
Register Mapping
Register
DMAC Global Configuration Register
DMAC Enable Register
DMAC Software Single Request Register
DMAC Software Chunk Transfer Request Register
DMAC Software Last Transfer Flag Register
Reserved
DMAC Error, Chained Buffer transfer completed and Buffer
transfer completed Interrupt Enable register.
DMAC Error, Chained Buffer transfer completed and Buffer
transfer completed Interrupt Disable register.
DMAC Error, Chained Buffer transfer completed and Buffer
transfer completed Mask Register.
DMAC Error, Chained Buffer transfer completed and Buffer
transfer completed Status Register.
DMAC Channel Handler Enable Register
DMAC Channel Handler Disable Register
DMAC Channel Handler Status Register
Reserved
Reserved
DMAC Channel Source Address Register
DMAC Channel Destination Address Register
DMAC Channel Descriptor Address Register
DMAC Channel Control A Register
DMAC Channel Control B Register
DMAC Channel Configuration Register
DMAC Channel Source Picture in Picture Configuration
Register
DMAC Channel Destination Picture in Picture Configuration
Register
Reserved
Reserved
DMAC Channel 1 to 7 Register
Reserved
(1)
0x140
.
Name
DMAC_GCFG
DMAC_EN
DMAC_SREQ
DMAC_CREQ
DMAC_LAST
–
DMAC_EBCIER
DMAC_EBCIDR
DMAC_EBCIMR
DMAC_EBCISR
DMAC_CHER
DMAC_CHDR
DMAC_CHSR
–
–
DMAC_SADDR
DMAC_DADDR
DMAC_DSCR
DMAC_CTRLA
DMAC_CTRLB
DMAC_CFG
DMAC_SPIP
DMAC_DPIP
–
–
–
Read-write
Access
Read-write
Read-write
Read-write
Read-write
Read-write
–
Write-only
Write-only
Read-only
Read-only
Write-only
Write-only
Read-only
–
–
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
–
–
Read-write
–
6438G–ATARM–19-Apr-11
Reset
0x10
0x0
0x0
0x0
0x0
–
–
–
0x0
0x0
–
–
0x00FF0000
–
–
0x0
0x0
0x0
0x0
0x0
0x01000000
0x0
0x0
–
–
0x0
–