SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 245

no-image

SAM9G45

Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G45

Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
Figure 22-17. Self Refresh Mode Entry, Timeout = 0
Figure 22-18. Self Refresh Mode Entry, Timeout = 1 or 2
6438G–ATARM–19-Apr-11
COMMAND
COMMAND
DQS[0:1]
DQS[1:0]
BA[1:0]
A[12:0]
DM[1:0]
BA[1:0]
SDCLK
DM[1:0]
D[15:0]
SDCLK
D[15:0]
A[12:0]
CKE
CKE
NOP READ
0
3
NOP READ
0
3
The low-power DDR-SDRAM must remain in self refresh mode for a minimum of TRFC periods
and may remain in self refresh mode for an indefinite period.
The DDR2-SDRAM must remain in self refresh mode for a minimum of TCKE periods and may
remain in self refresh mode for an indefinite period.
BST
BST
NOP
NOP
Da
Da
Db
Db
64 or 128
wait states
PRCHG
PRCHG
NOP
NOP
Trp
Trp
ARFSH NOP
ARFSH
Enter Self refresh
Mode
Enter Self refresh
Mode
SAM9G45
NOP
245

Related parts for SAM9G45