SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 1098

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

45.7
45.8
1098
Interrupts
Configuration Sequence
SAM9G45
The LCD Controller generates six different IRQs. All the IRQs are synchronized with the internal
LCD Core Clock. The IRQs are:
Each IRQ can be individually enabled, disabled or cleared, in the LCD_IER (Interrupt Enable
Register), LCD_IDR (Interrupt Disable Register) and LCD_ICR (Interrupt Clear Register) regis-
ters. The LCD_IMR register contains the mask value for each IRQ source and the LDC_ISR
contains the status of each IRQ source. A more detailed description of these registers can be
found in
The DMA Controller starts to transfer image data when the LCDC Core is activated (Write to
LCD_PWR field of PWRCON register). Thus, the user should configure the LCDC Core and
configure and enable the DMA Controller prior to activation of the LCD Controller. In addition,
the image data to be shows should be available when the LCDC Core is activated, regardless of
the value programmed in the GUARD_TIME field of the PWRCON register.
To disable the LCD Controller, the user should disable the LCDC Core and then disable the
DMA Controller. The user should not enable LIP again until the LCDC Core is in IDLE state. This
is checked by reading the LCD_BUSY bit in the PWRCON register.
The initialization sequence that the user should follow to make the LCDC work is:
• DMA Memory error IRQ. Generated when the DMA receives an error response from an AHB
• FIFO underflow IRQ. Generated when the Serializer tries to read a word from the FIFO when
• FIFO overwrite IRQ. Generated when the DMA Controller tries to write a word in the FIFO
• DMA end of frame IRQ. Generated when the DMA controller updates the Frame Base
• End of Line IRQ. This IRQ is generated when the LINEBLANK period of each line is reached
• End of Last Line IRQ. This IRQ is generated when the LINEBLANK period of the last line of
• Create or copy the first image to show in the display buffer memory.
• If a palletized mode is used, create and store a palette in the internal LCD Palette
• Configure the LCD Controller Core without enabling it:
slave while it is doing a data transfer.
the FIFO is empty.
while the FIFO is full.
Address pointers. This IRQ can be used to implement a double-buffer technique. For more
information, see
and the DMA Controller is in inactive state.
the current frame is reached and the DMA Controller is in inactive state.
memory(See “Palette” on page 1082.
– LCDCON1 register: Program the CLKVAL and BYPASS fields: these fields control the
pixel clock divisor that is used to generate the pixel clock LCDDOTCK. The value to
program depends on the LCD Core clock and on the type and size of the LCD
Module used. There is a minimum value of the LCDDOTCK clock period that
depends on the LCD Controller Configuration, this minimum value can be found in
Table 45-14 on page
pixel clock divisor can be found at the end of the section
“LCD Controller (LCDC) User Interface” on page
“Double-buffer Technique” on page
1087. The equations that are used to calculate the value of the
1100.
1103.
“Timegen” on page 1086
6438G–ATARM–19-Apr-11