SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 252

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

22.5
22.5.1
Table 22-1.
Table 22-2.
Table 22-3.
252
27
27
27
Bk[1:0]
26
26
26
Bk[1:0]
Bk[1:0]
Software Interface/SDRAM Organization, Address Mapping
SAM9G45
25
25
25
SDRAM Address Mapping for 16-bit Memory Data Bus Width
Bk[1:0]
Bk[1:0]
Bk[1:0]
24
24
24
Linear Mapping for SDRAM Configuration, 2K Rows, 512/1024/2048/4096 Columns
Linear Mapping for SDRAM Configuration: 4K Rows, 512/1024/2048/4096 Columns
Linear Mapping for SDRAM Configuration: 8K Rows, 512/1024/2048/4096 Columns
Bk[1:0]
Bk[1:0]
Bk[1:0]
23
23
23
Bk[1:0]
Bk[1:0]
22
22
22
Bk[1:0]
The SDRAM address space is organized into banks, rows and columns. The DDRSDRC maps
different memory types depending on the values set in the DDRSDRC Configuration Register.
See
trate the relation between CPU addresses and columns, rows and banks addresses for 16-bit
memory data bus widths and 32-bit memory data bus widths.
The DDRSDRC supports address mapping in linear mode .
Linear mode is a method for address mapping where banks alternate at each last SDRAM page
of current bank..
The DDRSDRC makes the SDRAM devices access protocol transparent to the user.
to
the device structure. Various configurations are illustrated.
21
21
21
Table 22-8
Section 22.7.3 “DDRSDRC Configuration Register” on page
20
20
20
Row[12:0]
Row[11:0]
19
19
19
Row[10:0]
Row[12:0]
Row[11:0]
illustrate the SDRAM device memory mapping seen by the user in correlation with
18
18
18
Row[10:0]
Row[12:0]
Row[11:0]
17
17
17
Row[10:0]
Row[12:0]
Row[11:0]
16
16
16
Row[10:0]
15
15
15
CPU Address Line
CPU Address Line
CPU Address Line
14
14
14
13
13
13
12
12
12
11
11
11
(1)
10
10
10
and Four Banks
9
9
9
8
8
8
Column[11:0]
Column[11:0]
Column[11:0]
7
Column[10:0]
7
Column[10:0]
7
Column[10:0]
258. The following figures illus-
Column[9:0]
Column[9:0]
Column[9:0]
6
6
6
Column[8:0]
Column[8:0]
Column[8:0]
5
5
5
4
4
4
6438G–ATARM–19-Apr-11
3
3
3
2
2
2
Table 22-1
1
1
1
M0
M0
M0
M0
M0
M0
M0
M0
M0
M0
M0
M0
0
0
0