SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 1085

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Table 45-13. Dithering Algorithm for Color Mode
6438G–ATARM–19-Apr-11
Frame
N+1
N+1
N+1
N+1
N+1
N+1
N+2
N+2
N+2
N+2
…
…
N
N
N
N
N
N
green_data_0
green_data_1
green_data_0
green_data_1
green_data_0
blue_data_0
blue_data_1
blue_data_0
blue_data_1
blue_data_0
red_data_0
red_data_1
red_data_0
red_data_1
red_data_0
red_data_1
Signal
…
…
Table 45-12. Dithering Algorithm for Monochrome Mode (Continued)
Consider now color display mode and two pixels p0 and p1 with the horizontal coordinates
4*n+0, and 4*n+1. A color pixel is composed of three components: {R, G, B}. Pixel p0 will be dis-
played sending the color components {R0, G0, B0} to the display. Pixel p1 will be displayed
sending the color components {R1, G1, B1}. Suppose that the data read from memory and
mapped to the lookup tables corresponds to shade level 10 for the three color components of
both pixels, with the dithering pattern to apply to all of them being DP2_3 = “1101 1011 0110”.
Table 45-13
Dual Scan Configuration, each panel data bus acts like in the equivalent single scan
configuration.)
Frame
Number
N+4
N+5
N+6
N+7
...
Shadow Level
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
1010
…
…
shows the output sequence in the data output bus for single scan configurations. (In
Pattern
1111
1010
0101
1010
...
Bit used
…
…
2
3
3
0
3
0
3
1
0
2
2
1
3
2
2
1
Pixel a
ON
ON
OFF
ON
...
Dithering Pattern
1011
1011
0110
0110
1101
1101
1101
1101
1101
1101
1011
1011
1011
1011
0110
0110
…
…
Pixel b
ON
OFF
ON
OFF
...
4-bit LCDD
LCDD[3]
LCDD[2]
LCDD[1]
LCDD[0]
LCDD[3]
LCDD[2]
LCDD[3]
LCDD[2]
LCDD[1]
LCDD[0]
LCDD[3]
LCDD[2]
LCDD[3]
LCDD[2]
LCDD[1]
LCDD[0]
…
…
Pixel c
ON
ON
OFF
ON
...
8-bit LCDD
LCDD[7]
LCDD[6]
LCDD[5]
LCDD[4]
LCDD[3]
LCDD[2]
LCDD[7]
LCDD[6]
LCDD[5]
LCDD[4]
LCDD[3]
LCDD[2]
LCDD[7]
LCDD[6]
LCDD[5]
LCDD[4]
…
…
SAM9G45
Pixel d
ON
OFF
ON
OFF
...
Output
G0
G1
G1
G0
R0
R1
B1
R0
B0
R1
B0
b0
g0
b1
…
…
r0
r1
1085