SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 932

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

40.11 Touch Screen ADC Controller (TSADCC) User Interface
Table 40-4.
932
Offset
0X5C
0x0C
0x1C
0x2C
0x3C
0x4C
0X60
0xE4
0xE8
0x00
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
0x30
0x34
0x38
0x40
0x44
0x48
0x50
0x54
0x58
SAM9G45
Register Mapping
Register
Control Register
Mode Register
Trigger Register
Touch Screen Register
Channel Enable Register
Channel Disable Register
Channel Status Register
Status Register
Last Converted Data Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Channel Data Register 0
Channel Data Register 1
Channel Data Register 2
Channel Data Register 3
Channel Data Register 4
Channel Data Register 5
Channel Data Register 6
Channel Data Register 7
X Position Data Register
Z1 Data Register
Z2 Data Register
Reserved
Manual Switch Command Register
Reserved
Write Protection Mode Register
Write Protection Status Register
TSADCC_WPMR
TSADCC_MSCR
TSADCC_WPSR
TSADCC_TRGR
TSADCC_CHER
TSADCC_CHDR
TSADCC_CHSR
TSADCC_LCDR
TSADCC_CDR0
TSADCC_CDR1
TSADCC_CDR2
TSADCC_CDR3
TSADCC_CDR4
TSADCC_CDR5
TSADCC_CDR6
TSADCC_CDR7
TSADCC_XPDR
TSADCC_Z1DR
TSADCC_Z2DR
TSADCC_TSR
TSADCC_IDR
TSADCC_IMR
TSADCC_IER
TSADCC_MR
TSADCC_CR
TSADCC_SR
Name
–
–
Read-write
Read-write
Read-write
Read-write
Read-write
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Access
–
–
6438G–ATARM–19-Apr-11
0x000C_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
–
–
–
–
–
–
–
–
–
–