SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 1180

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

1180
Doc. Rev
6438F
SAM9G45
Comments
Bus Matrix
- EBI_DRIVE and DDR_DRIVE bitfields edited in
- “12-layer” Matrix instead of “11-layer”
DDRSDRC
In
- TRTP bitfield reset value (0 --> 2) changed.
- 0 and 15’ cycles changed into ‘0 and 7’ in ”TRTP: Read to Precharge”.
- TXARD (-->2), TXARDS (-->6), and TRPA (-->0) reset values changed.
In
In
Electrical Characteristics
- Figure below
-
-
- Ultra low power Mode value changed in
-
Errata
-
-
-
-
- 3
ECC parity”
Nand Flash”
External Memories
- DQM0-3 added to
-
-
-
- On
LPDDR’ --> ‘DDRSDRC20’.
- All ‘DDR2SDRC’ changed into ‘DDRSDRC’.
Mechanical Characteristics
- New
- All ‘nominal’ changed into ‘typical’.
- An empty square after letter ‘V’ removed from the
PMC
- Note added to
Register”.
USART
- LIN Mode condition now shown in
Transmitter
Section 46.14 “DDRSDRC Timings”
Table 46-17 “I/O Characteristics”
Section 46.15.1.1 “Maximum SPI Frequency”
“Boot ROM”
“Static Memory Controller (SMC)”
“Touch Screen (TSADCC)”
“USB High Speed Host Port (UHPHS)”
Table
Section 20.2.7.7 “NAND Flash Support”
Section 20. “External Memories”
Section 22.7.6 “DDRSDRC Timing 2 Parameter
Section 22.7.7 “DDRSDRC Low-power
Section 22.4.4.1 “Self Refresh
“Error Corrected Code Controller (ECC)”
Figure 6-1 “SAM9G45 Memory
Figure 47-1 “324-ball TFBGA Package Drawing”
20-5, row ‘A15’ edited.
(USART)”.
,
“ECC: Unsupported ECC per 512 words”
errata added.
Table 46-7, “Main Oscillator Characteristics”
Section 25.4 “Master Clock
Figure 20-4 “EBI Connections to Memory
errata added.
Mode”, UDP_EN bitfield replaced by UPD_MR.
reorganized.
and Notes below edited.
errata added.
Section 33. “Universal Synchronous Asynchronous Receiver
Mapping”, ‘DDR2-LPDDR-SDRAM’ --> ‘DDRSDRC1’ and ‘DDR2-
updated.
errata added.
Table 46-3, “Power Consumption for Different
edited.
Register”, UPD_MR bitfield added to the table at [21:20].
Controller”and
errata added:
added.
“EBI Chip Select Assignment Register”
Register”,
Section 49.1 “Marking”
and
and Max. weight changed in
“ECC: Uncomplete parity status when error in
Section 25.12.12 “PMC Master Clock
“ECC: Unsupported hardware ECC on 16-bit
edited.
Devices”.
table.
Table 47-2
Modes”.
6438G–ATARM–19-Apr-11
Change
Request
Ref.
6930
7171
7134
7146
7063
7134 -7193
6926
7195
7173
7148
6977
7165
7194
7192
7123
7027
6924
6946
6954
RFO
7106
6944