SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 999

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

41.6.17
Name:
Addresses: 0xFFFFEC4C [0], 0xFFFFEC74 [1], 0xFFFFEC9C [2], 0xFFFFECC4 [3], 0xFFFFECEC [4],
Access:
Reset:
• SIF: Source Interface Selection Field
00: The source transfer is done via AHB-Lite Interface 0.
01: The source transfer is done via AHB-Lite Interface 1.
10: Reserved.
11: Reserved.
• DIF: Destination Interface Selection Field
00: The destination transfer is done via AHB-Lite Interface 0.
01: The destination transfer is done via AHB-Lite Interface 1.
10: Reserved.
11: Reserved.
• SRC_PIP
0: Picture-in-Picture mode is disabled. The source data area is contiguous.
1: Picture-in-Picture mode is enabled. When the source PIP counter reaches the programmable boundary, the address is
automatically increment of a user defined amount.
• DST_PIP
0: Picture-in-Picture mode is disabled. The Destination data area is contiguous.
1: Picture-in-Picture mode is enabled. When the Destination PIP counter reaches the programmable boundary the address
is automatically incremented by a user-defined amount.
• SRC_DSCR
0: Source address is updated when the descriptor is fetched from the memory.
1: Buffer Descriptor Fetch operation is disabled for the source.
6438G–ATARM–19-Apr-11
AUTO
31
23
15
–
7
–
DMAC Channel x [x = 0..7] Control B Register
DMAC_CTRLBx [x = 0..7]
0xFFFFED14 [5], 0xFFFFED3C [6], 0xFFFFED64 [7]
Read-write
0x00000000
IEN
FC
30
22
14
–
6
–
29
21
13
5
DST_INCR
DIF
DST_DSCR
DST_PIP
28
20
12
4
27
19
11
–
–
–
3
–
26
18
10
–
–
–
2
–
25
17
–
9
–
1
SRC_INCR
SAM9G45
SIF
SRC_DSCR
SRC_PIP
24
16
8
0
999