SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 1162

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Table 46-40. ISI Timings with 1.8V Peripheral Supply
46.15.4
46.15.5
46.15.5.1
46.15.5.2
Table 46-42. EMAC Signals Relative to EMDC
Notes:
1162
Symbol
ISI
ISI
ISI
Symbol
EMAC
EMAC
EMAC
1
2
3
1
2
3
1. For EMAC output signals, Min and Max access time are defined. The Min access time is the time between the EDMC falling
SAM9G45
HSMCI
EMAC
edge and the signal change. The Max access time is the time between the EDMC falling edge and the signal stabilization.
Figure 46-20
Timing Conditions
Timing Constraints
Parameter
DATA/VSYNC/HSYNC setup time
DATA/VSYNC/HSYNC hold time
PIXCLK frequency
Parameter
Setup for EMDIO from EMDC rising
Hold for EMDIO from EMDC rising
EMDIO toggling from EMDC falling
illustrates Min and Max accesses for EMAC3.
The High Speed MultiMedia Card Interface (HSMCI) supports the MultiMedia Card (MMC)
Specification V4.3, the SD Memory Card Specification V2.0, the SDIO V2.0 specification and
CE-ATA V1.1.
Timings are given assuming a capacitance load on data and clock:
Table 46-41. Capacitance Load on Data, Clock Pads
The Ethernet controller must satisfy the timings of MAX corner standards given in
and
Supply
3.3V
1.8V
Table
46-43.
MAX
20pF
20pF
Corner
MIN
0pF
0pF
Min
1.1
2.2
Max
80
Min (ns)
13.5
0
10
(1)
6438G–ATARM–19-Apr-11
Max (ns)
Units
ns
ns
MHz
Table 46-42
2
(1)