SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 134

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Table 19-4.
19.3
19.4
134
1
2
3
4
5
6
7
0
Internal SRAM 0
Memory Mapping
Special Bus Granting Mechanism
Master
Internal Periph.
Slave
LCD User Int.
UDPHS RAM
Internal ROM
SAM9G45
DDR Port 0
DDR Port 1
DDR Port 2
DDR Port 3
UHP OHCI
UHP EHCI
Reserved
EBI
Masters to Slaves Access with DDRMP_DIS = 1 (default)
926 Instr.
ARM
.
Table 19-5
the Remap status (RCBx bit in Bus Matrix Master Remap Control Register MATRIX_MRCR) and
the BMS state at reset.
Table 19-5.
The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each
AHB master several memory mappings. In fact, depending on the product, each memory area
may be assigned to several slaves. Booting at the same address while using different AHB
slaves (i.e. external RAM, internal ROM or internal Flash, etc.) becomes possible.
The Bus Matrix user interface provides Master Remap Control Register (MATRIX_MRCR) that
performs remap action for every master independently.
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access
requests from some masters. This mechanism reduces latency at first access of a burst or single
0
X
X
X
X
X
X
X
X
X
X
-
-
-
Base Address
0x0000 0000
926 Data
Slave
ARM
1
X
X
X
X
X
X
X
X
X
X
-
-
-
summarizes the Slave Memory Mapping for each connected Master, depending on
Internal Memory Mapping
PDC
2
X
X
X
X
X
X
-
-
-
-
-
-
-
HOST
Internal ROM
OHCI
USB
BMS = 1
3
X
X
X
X
-
-
-
-
-
-
-
-
-
4 & 5
DMA
X
X
X
X
X
-
-
-
-
-
-
-
-
RCBx = 0
DMA
ISI
6
X
X
X
X
-
-
-
-
-
-
-
-
-
EBI NCS0
BMS
Master
DMA
LCD
7
X
X
-
-
-
-
-
-
-
-
-
-
-
= 0
Ethernet
MAC
8
X
X
X
X
-
-
-
-
-
-
-
-
-
Device HS
Internal SRAM
USB
RCBx = 1
9
X
X
X
X
X
-
-
-
-
-
-
-
-
6438G–ATARM–19-Apr-11
USB Host
EHCI
10
X
X
X
X
-
-
-
-
-
-
-
-
-
Reserved
11
X
X
-
-
-
-
-
-
-
-
-
-
-