SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 420

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

29.6
29.6.1
29.6.2
29.6.3
29.6.4
420
Product Dependencies
SAM9G45
I/O Lines
Power Management
Interrupt
Peripheral DMA Controller (PDMA) Direct Memory Access Controller (DMAC)
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
The programmer must first program the PIO controllers to assign the SPI pins to their peripheral
functions.
Table 29-2.
The SPI may be clocked through the Power Management Controller (PMC), thus the program-
mer must first configure the PMC to enable the SPI clock.
The SPI interface has an interrupt line connected to the Advanced Interrupt Controller
(AIC).Handling the SPI interrupt requires programming the AIC before configuring the SPI.
Table 29-3.
The SPI interface can be used in conjunction with the PDMA DMAC in order to reduce processor
overhead. For a full description of the PDMA DMAC, refer to the corresponding section in the full
datasheet.
Instance
Instance
SPI0
SPI1
SPI0
SPI0
SPI0
SPI0
SPI0
SPI0
SPI0
SPI0
SPI0
SPI1
SPI1
SPI1
SPI1
SPI1
SPI1
SPI1
I/O Lines
Peripheral IDs
14
15
ID
SPI0_NPCS0
SPI0_NPCS1
SPI0_NPCS1
SPI0_NPCS2
SPI0_NPCS2
SPI0_NPCS3
SPI1_NPCS0
SPI1_NPCS1
SPI1_NPCS2
SPI1_NPCS3
SPI0_SPCK
SPI1_SPCK
SPI0_MISO
SPI0_MOSI
SPI1_MISO
SPI1_MOSI
Signal
I/O Line
PD24
PD25
PD27
PD28
PD18
PD19
PB18
PB19
PB14
PB15
PB17
PB16
PB0
PB1
PB3
PB2
6438G–ATARM–19-Apr-11
Peripheral
A
A
A
B
A
B
A
B
A
A
A
A
B
A
A
A