SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 644

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

34.7
Figure 34-4. SSC Functional Block Diagram
34.7.1
644
Functional Description
SAM9G45
oClock Management
APB
MCK
Interface
Divider
Clock
User
This chapter contains the functional description of the following: SSC Functional Block, Clock
Management, Data format, Start, Transmitter, Receiver and Frame Sync.
The receiver and transmitter operate separately. However, they can work synchronously by pro-
gramming the receiver to use the transmit clock and/or to start a data transfer when transmission
starts. Alternatively, this can be done by programming the transmitter to use the receive clock
and/or to start a data transfer when reception starts. The transmitter and the receiver can be pro-
grammed to operate with the clock signals provided on either the TK or RK pins. This allows the
SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TK
and RK pins is the master clock divided by 2.
The transmitter clock can be generated by:
• an external clock received on the TK I/O pad
• the receiver clock
Interrupt Control
AIC
RXEN
TX Start
RF
RC0R
TXEN
RX Start
TF
TX Clock
TK Input
RK Input
RX clock
Selector
Selector
Start
Start
Receive Holding
Transmit Holding
Register
Register
Transmitter
Transmit Clock
Receive Shift Register
TX Start
Receive Clock
Transmit Shift Register
Controller
Controller
Receiver
RX Start
Holding Register
Holding Register
RX Clock
Receive Sync
TX clock
Transmit Sync
Clock Output
Frame Sync
Frame Sync
Clock Output
Controller
Controller
Controller
Controller
Controller
Controller
Data
Data
6438G–ATARM–19-Apr-11
RD
TD
RK
RF
TK
TF