SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 1079

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 45-2. Datapath Structure
6438G–ATARM–19-Apr-11
This module transforms the data read from the memory into a format according to the LCD mod-
ule used. It has four different interfaces: the input interface, the output interface, the
configuration interface and the control interface.
The datapath can be characterized by two parameters: initial_latency and cycles_per_data. The
parameter initial_latency is defined as the number of LCDC Core Clock cycles until the first data
is available at the output of the datapath. The parameter cycles_per_data is the minimum num-
ber of LCDC Core clock cycles between two consecutive data at the output interface.
• The input interface connects the datapath with the DMA controller. It is a dual FIFO interface
• The output interface is a 24-bit data bus. The configuration of this interface depends on the
• The configuration interface connects the datapath with the configuration block. It is used to
• The control interface connects the datapath with the timing generation block. The main
with a data bus and two push lines that are used by the DMA controller to fill the FIFOs.
type of LCD used (TFT or STN, Single or Dual Scan, 4-bit, 8-bit, 16-bit or 24-bit interface).
select between the different datapath configurations.
control signal is the data-request signal, used by the timing generation module to request
new data from the datapath.
Serializer
Dithering
Palette
Output
Shifter
FIFO
Input Interface
Output Interface
Configuration IF
Control Interface
SAM9G45
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