SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 1039

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

43.7.3.7
43.7.3.8
43.7.3.9
43.7.3.10
6438G–ATARM–19-Apr-11
31
31
31
31
31
31
Byte0[7:0]
Endianness
To Transmit a Word Stored in Big Endian Format on AC-link
To Transmit A Halfword Stored in Big Indian Format on AC-link
To Transmit a10-bit Sample Stored in Big Endian Format on AC-link
–
–
–
–
–
The application can disable event interrupts by writing in AC97 Controller Interrupt Disable Reg-
ister (AC97C_IDR). The AC97 Controller Interrupt Mask Register (AC97C_IMR) shows which
event can trigger an interrupt and which one cannot.
Endianness can be managed automatically for each channel, except for the Codec channel, by
writing to Channel Endianness Mode (CEM) in AC97C_CxMR. This enables transferring data on
AC-link in Big Endian format without any additional operation.
Word to be written in AC97 Controller Channel x Transmit Holding Register (AC97C_CxTHR)
(as it is stored in memory or microprocessor register).
Word stored in Channel x Transmit Holding Register (AC97C_CxTHR) (data to transmit)
Data transmitted on appropriate slot: data[19:0] = {Byte2[3:0], Byte1[7:0], Byte0[7:0]}.
Halfw ord to be written in AC97 Controlle r Channel x Transmit Holding Register
(AC97C_CxTHR).
Halfword stored in AC97 Controller Channel x Transmit Holding Register (AC97C_CxTHR) (data
to transmit).
Data emitted on related slot: data[19:0] = {0x0, Byte1[7:0], Byte0[7:0]}.
Halfw ord to be written in AC97 Controlle r Channel x Transmit Holding Register
(AC97C_CxTHR).
Halfword stored in AC97 Controller Channel x Transmit Holding Register (AC97C_CxTHR) (data
to transmit).
Data emitted on related slot: data[19:0] = {0x000, Byte1[1:0], Byte0[7:0]}.
24
24
24
24
24
24
23
23
23
23
23
23
–
Byte1[7:0]
20
–
–
–
–
19
Byte2[3:0]
16
16
16
16
16
16
15
15
15
15
15
15
–
Byte1[7:0]
Byte1[7:0]
Byte2[7:0]
Byte0[7:0]
Byte0[7:0]
10
Byte1
9
[1:0]
8
8
8
8
8
8
7
7
7
7
7
7
{0x00, Byte1[1:0]}
Byte3[7:0]
Byte0[7:0]
Byte1[7:0]
Byte0[7:0]
Byte0[7:0]
SAM9G45
.
1039
0
0
0
0
0
0